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C161U
Central Processor Unit
Preliminary Data Sheet
65
02.2000
PRELIMINARY
PRE
LI
M
INAR
Y
- E
XCE
RP
T
-
updated by an immediately preceding instruction. Thus, to make sure that the new DPPn
register value is used, at least one instruction must be inserted between a DPPn-
changing instruction and a subsequent instruction which implicitly uses DPPn via a long
or indirect addressing mode, as shown in the following example:
I
n
: MOV DPP0, #4
; select data page 4 via DPP0
I
n+1
: ....
; must not be an instruction using DPP0
I
n+2
: MOV DPP0:0000H, R1
; move contents of R1 to address location 01’0000
H
; (in data page 4) supposed segmentation is enabled
Explicit Stack Pointer Updating
None of the RET, RETI, RETS, RETP or POP instructions is capable of correctly using
a new SP register value, which is to be updated by an immediately preceding instruction.
Thus, in order to use the new SP register value without erroneously performed stack
accesses, at least one instruction must be inserted between an explicitly SP-writing and
any subsequent of the just mentioned implicitly SP-using instructions, as shown in the
following example:
I
n
: MOV SP, #0FA40H
; select a new top of stack
I
n+1
: ....
; must not be an instruction popping operands
; from the system stack
I
n+2
: POP R0
; pop word value from new top of stack into R0
Note: Conflicts with instructions writing to the stack (PUSH, CALL, SCXT) are solved
internally by the CPU logic.
External Memory Access Sequences
The effect described here will only become noticeable, when watching the external
memory access sequences on the external bus (eg. by means of a Logic Analyzer).
Different pipeline stages can simultaneously put a request on the External Bus Controller
(EBC). The sequence of instructions processed by the CPU may diverge from the
sequence of the corresponding external memory accesses performed by the EBC, due
to the predefined priority of external memory accesses:
1st
Write Data
2nd Fetch Code
3rd
Read Data.
Controlling Interrupts
Software modifications (implicit or explicit) of the PSW are done in the execute phase of
the respective instructions. In order to maintain fast interrupt responses, however, the
current interrupt prioritization round does not consider these changes, ie. an interrupt
request may be acknowledged after the instruction that disables interrupts via IEN or
ILVL or after the following instructions. Timecritical instruction sequences therefore