C161U
Central Processor Unit
Preliminary Data Sheet
87
02.2000
PRELIMINARY
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The Multiply/Divide Low Register MDL
This register is a part of the 32-bit multiply/divide register, which is implicitly used by the
CPU, when it performs a multiplication or a division. After a multiplication, this non-bit
addressable register represents the low order 16 bits of the 32-bit result. For long
divisions, the MDL register must be loaded with the low order 16 bits of the 32-bit
dividend before the division is started. After any division, register MDL represents the 16-
bit quotient.
MDL (FE0E
H / 07H)
SFR
Reset Value: 0000
H
Whenever this register is updated via software, the Multiply/Divide Register In Use
(MDRIU) flag in the Multiply/Divide Control register (MDC) is set to '1'. The MDRIU flag
is cleared, whenever the MDL register is read via software.
When a multiplication or division is interrupted before its completion and when a new
multiply or divide operation is to be performed within the interrupt service routine, register
MDL must be saved along with registers MDH and MDC to avoid erroneous results.
A detailed description of how to use the MDL register for programming multiply and
divide algorithms can be found in chapter “System Programming”.
The Multiply/Divide Control Register MDC
This bit addressable 16-bit register is implicitly used by the CPU, when it performs a
multiplication or a division. It is used to store the required control information for the
corresponding multiply or divide operation. Register MDC is updated by hardware during
each single cycle of a multiply or divide instruction.
MDC (FF0E
H / 87H)
SFR
Reset Value: 0000
H
When a division or multiplication was interrupted before its completion and the multiply/
divide unit is required, the MDC register must first be saved along with registers MDH
Bit
Function
mdl
Specifies the low order 16 bits of the 32-bit multiply and divide register MD.
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15
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rw
mdl
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r(w)
MDR
IU