C161U
Power Reduction Modes
Preliminary Data Sheet
379
02.2000
PRELIMINARY
PRE
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XCE
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The Sleep mode is controlled by bitfield SLEEPCON within register SYSCON1.
SYSCON1 (F1DCH / EEH)
ESFR-b
Reset Value: 0000H
Note: SYSCON1 is write protected after the execution of EINIT unless it is released via
the unlock sequence.
General description of SYSCON1 bits:
Before entering Sleep mode with the IDLE instruction, the continuation of instruction
processing after termination of Sleep mode must be prepared as known from standard
Idle mode. For wakeup with interrupt, four general possibilities of continuation can be
selected, which are controlled (prepared) as follows:
Continuation with first instruction after the IDLE instruction will be enabled if
– interrupts are globally disabled with the Interrupt Enable bit in PSW, or
– the interrupt is enabled by global (PSW) and by individual (interrupt control register)
enable bit, but the current CPU priority level (in PSW) of IDLE instruction is higher
than the interrupt level.
Continuation with first instruction of dedicated interrupt service routine will be
selected if
the interrupt is enabled by global (in PSW) and by individual (interrupt control register)
enable bit, and the CPU priority level of IDLE instruction is lower than the interrupt
level, thus the enabled interrupt has highest priority. Additionally, PEC Transfer for this
interrupt is not enabled. The continuation with the dedicated service routine is always
performed in case of NMI hardware traps, independently of any enable bit or CPU
priority level.
Execution of one PEC Transfer and resumption of Sleep mode will be selected if
the interrupt is enabled by global (in PSW) and by individual (interrupt control register)
enable bit, and the CPU priority level of IDLE instruction is lower than the interrupt
level, thus the enabled interrupt has highest priority. Additionally, PEC Transfer for this
interrupt is enabled.
Bit
Function
SLEEPCON
SLEEP Mode Configuration
‘0 0’:
normal IDLE mode
‘0 1’:
SLEEP mode with running RTC
‘1 0’:
reserved
‘1 1’:
SLEEP mode with stopped RTC and stopped OSC
-
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
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SLEEPCON
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