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参数资料
| 型号： | MT48H32M16LFB4-75B IT:C |
| 厂商： | Micron Technology Inc |
| 文件页数： | 21/85页 |
| 文件大小： | 0K |
| 描述： | IC SDRAM 512MB 54VFBGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 SDRAM |
| 存储容量： | 512M（32Mx16） |
| 速度： | 133MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 54-VFBGA |
| 供应商设备封装： | 54-VFBGA（8x8） |
| 包装： | 散装 |
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Electrical Specifications – AC Operating Conditions
Table 13: AC Functional Characteristics
Notes 1–5 apply to all parameters and conditions
Parameter
Last data-in to burst STOP command
READ/WRITE command to READ/WRITE command
Last data-in to new READ/WRITE command
CKE to clock disable or power-down entry mode
Data-in to ACTIVE command
Data-in to PRECHARGE command
DQM to input data delay
DQM to data mask during WRITEs
DQM to data High-Z during READs
WRITE command to input data delay
LOAD MODE REGISTER command to ACTIVE or REFRESH command
CKE to clock enable or power-down exit mode
Last data-in to PRECHARGE command
Symbol
t BDL
t CCD
t CDL
t CKED
t DAL
t DPL
t DQD
t DQM
t DQZ
t DWD
t MRD
t PED
t RDL
-6
1
1
1
1
5
2
0
0
2
0
2
1
2
-75
1
1
1
1
5
2
0
0
2
0
2
1
2
Units
t CK
t CK
t CK
t CK
t CK
t CK
t CK
t CK
t CK
t CK
t CK
t CK
t CK
Notes
13
13
14
14
15, 17
16, 17
13
13
13
13
14
16, 17
Data-out High-Z from PRECHARGE command
CL = 3
t ROH
3
3
t CK
13
CL = 2
2
2
t CK
Notes:
1. A full initialization sequence is required before proper device operation is ensured.
2. The minimum specifications are used only to indicate cycle time at which proper opera-
tion over the full temperature range (0?C ≤ T A ≤ +70?C standard temperature and –40?C
≤ T A ≤ +85?C industrial temperature) is ensured.
3. In addition to meeting the transition rate specification, the clock and CKE must transit
between V IH and V IL (or between V IL and V IH ) in a monotonic manner.
4. Outputs measured for 1.8V at 0.9V with equivalent load:
Q
20pF
Test loads with full DQ driver strength. Performance will vary with actual system DQ bus
capacitive loading, termination, and programmed drive strength.
5.
6.
7.
8.
9.
AC timing tests have V IL and V IH with timing referenced to V IH/2 = crossover point. If the
input transition time is longer than t Tmax, then the timing is referenced at V IL,max and
V IH,min and no longer at the V IH /2 crossover point.
The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock ball) during access or precharge states
(READ, WRITE, including t WR, and PRECHARGE commands). CKE may be used to reduce
the data rate.
t HZ defines the time at which the output achieves the open circuit condition, it is not a
reference to V OH or V OL . The last valid data element will meet t OH before going High-Z.
DRAM devices should be evenly addressed when being accessed. Disproportionate ac-
cesses to a particular row address may result in reduction of the product lifetime.
This device requires 8192 AUTO REFRESH cycles every 64ms ( t REF). Providing a distrib-
uted AUTO REFRESH command every 7.8125 μ s meets the refresh requirement and en-
sures that each row is refreshed. Alternatively, 8192 AUTO REFRESH commands can be
issued in a burst at the minimum cycle rate ( t RFC), once every 64ms.
PDF: 09005aef8459c827
512mb_mobile_sdram_y67m_at.pdf – Rev. B 3/11 EN
21
Micron Technology, Inc. reserves the right to change products or specifications without notice.
? 2011 Micron Technology, Inc. All rights reserved.
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