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参数资料
| 型号： | MT48H32M16LFB4-75B IT:C |
| 厂商： | Micron Technology Inc |
| 文件页数： | 50/85页 |
| 文件大小： | 0K |
| 描述： | IC SDRAM 512MB 54VFBGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 SDRAM |
| 存储容量： | 512M（32Mx16） |
| 速度： | 133MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 54-VFBGA |
| 供应商设备封装： | 54-VFBGA（8x8） |
| 包装： | 散装 |
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
READ Operation
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 19
(page 50) shows where, due to the clock cycle frequency, bus contention is avoided
without having to add a NOP cycle, while Figure 20 (page 51) shows the case where an
additional NOP cycle is required.
A fixed-length READ burst may be followed by or truncated with a PRECHARGE com-
mand to the same bank, provided that auto precharge was not activated. The PRE-
CHARGE command should be issued x cycles before the clock edge at which the last de-
sired data element is valid, where x = CL - 1. This is shown in Figure 21 (page 51) for
each possible CL; data element n + 3 is either the last of a burst of four or the last de-
sired data element of a longer burst. Following the PRECHARGE command, a subse-
quent command to the same bank cannot be issued until t RP is met. Note that part of
the row precharge time is hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE com-
mand issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvant-
age of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command. The advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or continuous
page bursts.
Figure 19: READ-to-WRITE
T0
T1
T2
T3
T4
CLK
DQM
Command
READ
NOP
NOP
NOP
WRITE
Address
Bank,
Col n
tCK
tHZ
Bank,
Col b
DS
DQ
Transitioning data
D OUT n
D IN b
t
Don’t Care
Note:
1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be
to any bank. If a burst of one is used, DQM is not required.
PDF: 09005aef8459c827
512mb_mobile_sdram_y67m_at.pdf – Rev. B 3/11 EN
50
Micron Technology, Inc. reserves the right to change products or specifications without notice.
? 2011 Micron Technology, Inc. All rights reserved.
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