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参数资料
| 型号： | MT48H32M16LFB4-75B IT:C |
| 厂商： | Micron Technology Inc |
| 文件页数： | 47/85页 |
| 文件大小： | 0K |
| 描述： | IC SDRAM 512MB 54VFBGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 SDRAM |
| 存储容量： | 512M（32Mx16） |
| 速度： | 133MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 54-VFBGA |
| 供应商设备封装： | 54-VFBGA（8x8） |
| 包装： | 散装 |
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
READ Operation
READ Operation
READ bursts are initiated with a READ command, as shown in Figure 9 (page 29). The
starting column and bank addresses are provided with the READ command, and auto
precharge is either enabled or disabled for that burst access. If auto precharge is ena-
bled, the row being accessed is precharged at the completion of the burst. In the follow-
ing figures, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address is
available following the CAS latency after the READ command. Each subsequent data-
out element will be valid by the next positive clock edge. Figure 18 (page 49) shows
general timing for each possible CAS latency setting.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
signals will go to High-Z. A continuous page burst continues until terminated. At the
end of the page, it wraps to column 0 and continues.
Data from any READ burst can be truncated with a subsequent READ command, and
data from a fixed-length READ burst can be followed immediately by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst either follows the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ com-
mand should be issued x cycles before the clock edge at which the last desired data ele-
ment is valid, where x = CL - 1. This is shown in Figure 18 (page 49) for CL2 and CL3.
Mobile LPSDR devices use a pipelined architecture and therefore do not require the 2 n
rule associated with a prefetch architecture. A READ command can be initiated on any
clock cycle following a READ command. Full-speed random read accesses can be per-
formed to the same bank, or each subsequent READ can be performed to a different
bank.
PDF: 09005aef8459c827
512mb_mobile_sdram_y67m_at.pdf – Rev. B 3/11 EN
47
Micron Technology, Inc. reserves the right to change products or specifications without notice.
? 2011 Micron Technology, Inc. All rights reserved.
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