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| 型号： | MT48H32M16LFB4-75B IT:C |
| 厂商： | Micron Technology Inc |
| 文件页数： | 40/85页 |
| 文件大小： | 0K |
| 描述： | IC SDRAM 512MB 54VFBGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 SDRAM |
| 存储容量： | 512M（32Mx16） |
| 速度： | 133MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 54-VFBGA |
| 供应商设备封装： | 54-VFBGA（8x8） |
| 包装： | 散装 |
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Mode Register
Mode Register
The mode register defines the specific mode of operation, including burst length (BL),
burst type, CAS latency (CL), operating mode, and write burst mode. The mode register
is programmed via the LOAD MODE REGISTER command and retains the stored infor-
mation until it is programmed again or the device loses power.
Mode register bits M[2:0] specify the BL; M3 specifies the type of burst; M[6:4] specify
the CL; M7 and M8 specify the operating mode; M9 specifies the write burst mode; and
M10–M n should be set to zero to ensure compatibility with future revisions. M n + 1 and
M n + 2 should be set to zero to select the mode register.
The mode registers must be loaded when all banks are idle, and the controller must wait
t MRD before initiating the subsequent operation. Violating either of these requirements
will result in unspecified operation.
Figure 13: Mode Register Definition
BA1 BA0 An
...
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
A0
Address bus
Mn+2 Mn+1 Mn
n+2 n+1 n
...
...
M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
10 9 8 7 6 5 4 3 2 1 0
Mode
register (Mx)
0
0
Reserved*
WB Op mode CAS latency
BT
Burst length
Mn+2 Mn+1 Mode Register Definition
Burst Length
0
0
Base mode register
M2 M1 M0
M3 = 0
M3 = 1
0
1
1
1
0
1
Reserved
Extended mode register
Reserved
0
0
0
0
0
1
0
1
0
1
2
4
1
2
4
0
1
1
8
8
M9
0
1
Write Burst Mode
Programmed burst length
Single location access
1
1
1
1
0
0
1
1
0
1
0
1
Reserved
Reserved
Reserved
Continuous
Reserved
Reserved
Reserved
Reserved
M8 M7
Operating Mode
0
0
Normal operation
–
–
All other states reserved
M6 M5 M4
0 0 0
CAS Latency
Reserved
M3
0
1
Burst Type
Sequential
Interleaved
PDF: 09005aef8459c827
512mb_mobile_sdram_y67m_at.pdf – Rev. B 3/11 EN
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
40
*Should be programmed to 0
to ensure compatibility
with future devices.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
? 2011 Micron Technology, Inc. All rights reserved.
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