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参数资料
| 型号： | MT48H32M16LFB4-75B IT:C |
| 厂商： | Micron Technology Inc |
| 文件页数： | 26/85页 |
| 文件大小： | 0K |
| 描述： | IC SDRAM 512MB 54VFBGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 SDRAM |
| 存储容量： | 512M（32Mx16） |
| 速度： | 133MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 54-VFBGA |
| 供应商设备封装： | 54-VFBGA（8x8） |
| 包装： | 散装 |
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512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Functional Description
Functional Description
Mobile LPSDR devices are quad-bank DRAM that operate at 1.8V and include a syn-
chronous interface. All signals are registered on the positive edge of the clock signal,
CLK.
Read and write accesses to the device are burst oriented; accesses start at a selected lo-
cation and continue for a programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE command, followed by a
READ or WRITE command. The address bits registered coincident with the ACTIVE
command are used to select the bank and row to be accessed (BA0 and BA1 select the
bank). The address bits registered coincident with the READ or WRITE command are
used to select the starting column location for the burst access.
The device provides for programmable READ or WRITE burst lengths. An auto pre-
charge function may be enabled to provide a self-timed row precharge that is initiated
at the end of the burst sequence.
The device uses an internal pipelined architecture that enables changing the column
address on every clock cycle to achieve high-speed, fully random access. Precharging
one bank while accessing one of the other three banks will hide the precharge cycles.
The device is designed to operate in 1.8V memory systems. An auto refresh mode is pro-
vided, along with power-saving, power-down, and deep power-down modes. All inputs
and outputs are LVTTL-compatible.
The device offers substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks in order to hide precharge
time, and the capability to randomly change column addresses on each clock cycle dur-
ing a burst access.
PDF: 09005aef8459c827
512mb_mobile_sdram_y67m_at.pdf – Rev. B 3/11 EN
26
Micron Technology, Inc. reserves the right to change products or specifications without notice.
? 2011 Micron Technology, Inc. All rights reserved.
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