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型号： XC3S700A-4FT256I
厂商： Xilinx Inc
文件页数： 49/132页
文件大小： 0K
描述： IC FPGA SPARTAN 3 256FTBGA
标准包装： 90
系列： Spartan®-3A
LAB/CLB数： 1472
逻辑元件/单元数： 13248
RAM 位总计： 368640
输入/输出数： 161
门数： 700000
电源电压： 1.14 V ~ 1.26 V
安装类型： 表面贴装
工作温度： -40°C ~ 100°C
封装/外壳： 256-LBGA
供应商设备封装： 256-FTBGA
DC and Switching Characteristics
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
23
Pin-to-Pin Setup and Hold Times
Table 19: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Symbol
Description
Conditions
Device
Speed Grade
Units
-5
-4
Min
Setup Times
TPSDCM
When writing to the Input
Flip-Flop (IFF), the time from the
setup of data at the Input pin to
the active transition at a Global
Clock pin. The DCM is in use. No
Input Delay is programmed.
LVCMOS25(2),
IFD_DELAY_VALUE = 0,
with DCM(4)
XC3S50A
2.45
2.68
ns
XC3S200A
2.59
2.84
ns
XC3S400A
2.38
2.68
ns
XC3S700A
2.38
2.57
ns
XC3S1400A
1.91
2.17
ns
TPSFD
When writing to IFF, the time from
the setup of data at the Input pin
to an active transition at the
Global Clock pin. The DCM is not
in use. The Input Delay is
programmed.
LVCMOS25(2),
IFD_DELAY_VALUE = 5,
without DCM
XC3S50A
2.55
2.76
ns
XC3S200A
2.32
2.76
ns
XC3S400A
2.21
2.60
ns
XC3S700A
2.28
2.63
ns
XC3S1400A
2.33
2.41
ns
Hold Times
TPHDCM
When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is in use. No Input Delay is
programmed.
LVCMOS25(3),
IFD_DELAY_VALUE = 0,
with DCM(4)
XC3S50A
-0.36
ns
XC3S200A
-0.52
ns
XC3S400A
-0.33
-0.29
ns
XC3S700A
-0.17
-0.12
ns
XC3S1400A
-0.07
0.00
ns
TPHFD
When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is not in use. The Input
Delay is programmed.
LVCMOS25(3),
IFD_DELAY_VALUE = 5,
without DCM
XC3S50A
-0.63
-0.58
ns
XC3S200A
-0.56
ns
XC3S400A
-0.42
ns
XC3S700A
-0.80
-0.75
ns
XC3S1400A
-0.69
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 23. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 23. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
4.
DCM output jitter is included in all measurements.
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