参数资料
型号: XC3S700A-4FT256I
厂商: Xilinx Inc
文件页数: 62/132页
文件大小: 0K
描述: IC FPGA SPARTAN 3 256FTBGA
标准包装: 90
系列: Spartan®-3A
LAB/CLB数: 1472
逻辑元件/单元数: 13248
RAM 位总计: 368640
输入/输出数: 161
门数: 700000
电源电压: 1.14 V ~ 1.26 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 256-LBGA
供应商设备封装: 256-FTBGA
DC and Switching Characteristics
DS529-3 (v2.0) August 19, 2010
35
Differential Standards
LVDS_25
1.16
ns
LVDS_33
0.46
ns
BLVDS_25
0.11
ns
MINI_LVDS_25
0.75
ns
MINI_LVDS_33
0.40
ns
LVPECL_25
Input Only
LVPECL_33
RSDS_25
1.42
ns
RSDS_33
0.58
ns
TMDS_33
0.46
ns
PPDS_25
1.07
ns
PPDS_33
0.63
ns
DIFF_HSTL_I_18
0.43
ns
DIFF_HSTL_II_18
0.41
ns
DIFF_HSTL_III_18
0.36
ns
DIFF_HSTL_I
1.01
ns
DIFF_HSTL_III
0.54
ns
DIFF_SSTL18_I
0.49
ns
DIFF_SSTL18_II
0.41
ns
DIFF_SSTL2_I
0.82
ns
DIFF_SSTL2_II
0.09
ns
DIFF_SSTL3_I
1.16
ns
DIFF_SSTL3_II
0.28
ns
Notes:
1.
The numbers in this table are tested using the methodology
presented in Table 27 and are based on the operating conditions
set forth in Table 8, Table 11, and Table 13.
2.
These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.
3.
Note that 16 mA drive is faster than 24 mA drive for the Slow
slew rate.
Table 26: Output Timing Adjustments for IOB(Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Units
Speed Grade
-5
-4
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