- 您现在的位置：买卖IC网 > PDF目录262949 > MT46H16M32LFB5-6IT:C 16M X 32 DDR DRAM, PBGA90 PDF资料下载
参数资料
| 型号： | MT46H16M32LFB5-6IT:C |
| 元件分类： | DRAM |
| 英文描述： | 16M X 32 DDR DRAM, PBGA90 |
| 封装： | 13 X 8 MM, GREEN, PLASTIC, VFBGA-90 |
| 文件页数： | 29/95页 |
| 文件大小： | 3228K |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页
Table 17: DM Operation Truth Table
Name (Function)
DM
DQ
Notes
Write enable
L
Valid
Write inhibit
H
X
Notes: 1. Used to mask write data; provided coincident with the corresponding data.
2. All states and sequences not shown are reserved and/or illegal.
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the device. Operations already in progress are not affected.
NO OPERATION
The NO OPERATION (NOP) command is used to instruct the selected device to perform
a NOP. This prevents unwanted commands from being registered during idle or wait
states. Operations already in progress are not affected.
LOAD MODE REGISTER
The mode registers are loaded via inputs A[0:n]. See mode register descriptions in Stand-
MODE REGISTER command can only be issued when all banks are idle, and a subse-
quent executable command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to activate a row in a particular bank for a subsequent
access. The values on the BA0 and BA1 inputs select the bank, and the address provided
on inputs A[0:n] selects the row. This row remains active for accesses until a PRE-
CHARGE command is issued to that bank. A PRECHARGE command must be issued
before opening a different row in the same bank.
Micron Confidential and Proprietary
Advance
512Mb: x16, x32 Mobile LPDDR SDRAM
Commands
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. B 2/10 EN
35
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
相关PDF资料 |
PDF描述 |
|---|---|
| ML1I-65656L-100CB | 32K X 8 STANDARD SRAM, 100 ns, CDIP28 |
| M95160-MB6TP | 2K X 8 SPI BUS SERIAL EEPROM, DSO8 |
| M95160-WMB3T | 2K X 8 SPI BUS SERIAL EEPROM, DSO8 |
| MT45W2MV16BAFB-601WT | 2M X 16 PSEUDO STATIC RAM, 60 ns, PBGA54 |
| MT45W2MV16BAFB-706LIT | 2M X 16 PSEUDO STATIC RAM, 70 ns, PBGA54 |
相关代理商/技术参数 |
参数描述 |
|---|
发布紧急采购，3分钟左右您将得到回复。