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| 型号： | MT46H16M32LFB5-6IT:C |
| 元件分类： | DRAM |
| 英文描述： | 16M X 32 DDR DRAM, PBGA90 |
| 封装： | 13 X 8 MM, GREEN, PLASTIC, VFBGA-90 |
| 文件页数： | 38/95页 |
| 文件大小： | 3228K |
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Table 19: Truth Table – Current State Bank n – Command to Bank m (Continued)
Notes 1–6 apply to all parameters in this table
Current State
CS#
RAS#
CAS#
WE# Command/Action
Notes
Read (with auto
precharge)
L
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column and start new READ burst)
L
H
L
WRITE (select column and start WRITE burst)
L
H
L
PRECHARGE
Write (with auto
precharge)
L
H
ACTIVE (select and activate row)
L
H
L
H
READ (select column and start READ burst)
L
H
L
WRITE (select column and start new WRITE burst)
L
H
L
PRECHARGE
Notes: 1. This table applies when CKEn - 1 was HIGH, CKEn is HIGH and after tXSR has been met (if
the previous state was self refresh), after tXP has been met (if the previous state was power-
down, or a full initialization if the previous state was deep power-down).
2. This table describes alternate bank operation, except where noted (for example, the cur-
rent state is for bank n and the commands shown are those supported for issue to bank
m, assuming that bank m is in such a state that the given command is supported). Excep-
tions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read: A READ burst has been initiated and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated and has not yet terminated or been terminated.
3a. Both the read with auto precharge enabled state or the write with auto precharge
enabled state can be broken into two parts: the access period and the precharge period.
For read with auto precharge, the precharge period is defined as if the same burst was
executed with auto precharge disabled and then followed with the earliest possible PRE-
CHARGE command that still accesses all of the data in the burst. For write with auto
precharge, the precharge period begins when tWR ends, with tWR measured as if auto
precharge was disabled. The access period starts with registration of the command and
ends when the precharge period (or tRP) begins. This device supports concurrent auto
precharge such that when a read with auto precharge is enabled or a write with auto
precharge is enabled, any command to other banks is supported, as long as that com-
mand does not interrupt the read or write data transfer already in process. In either
case, all other related limitations apply (i.e., contention between read data and write
data must be avoided).
3b. The minimum delay from a READ or WRITE command (with auto precharge enabled)
to a command to a different bank is summarized below.
From
Command
To Command
Minimum Delay
(with Concurrent Auto
Precharge)
WRITE with
Auto Precharge
READ or READ with auto precharge
WRITE or WRITE with auto precharge
PRECHARGE
ACTIVE
[1 + (BL/2)] tCK + tWTR
(BL/2) tCK
1 tCK
Micron Confidential and Proprietary
Advance
512Mb: x16, x32 Mobile LPDDR SDRAM
Truth Tables
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. B 2/10 EN
43
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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