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参数资料
| 型号： | MT46H16M32LFB5-6IT:C |
| 元件分类： | DRAM |
| 英文描述： | 16M X 32 DDR DRAM, PBGA90 |
| 封装： | 13 X 8 MM, GREEN, PLASTIC, VFBGA-90 |
| 文件页数： | 47/95页 |
| 文件大小： | 3228K |
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tions that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4,
8, or 16 locations are available for both sequential and interleaved burst types.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap when a boundary is reached. The block is uniquely
selected by A[i:1] when BL = 2, by A[i:2] when BL = 4, by A[i:3] when BL = 8, and by A[i:4]
when BL = 16, where Ai is the most significant column address bit for a given configura-
tion. The remaining (least significant) address bits are used to specify the starting
location within the block. The programmed burst length applies to both READ and
WRITE bursts.
Burst Type
Accesses within a given burst can be programmed to be either sequential or interleaved
via the standard mode register.
The ordering of accesses within a burst is determined by the burst length, the burst
type, and the starting column address.
Table 21: Burst Definition Table
Burst
Length
Starting Column Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
2
A0
0
0-1
1
1-0
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
16
A3
A2
A1
A0
Micron Confidential and Proprietary
Advance
512Mb: x16, x32 Mobile LPDDR SDRAM
Standard Mode Register
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. B 2/10 EN
51
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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