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参数资料
| 型号： | MT46H16M32LFB5-6IT:C |
| 元件分类： | DRAM |
| 英文描述： | 16M X 32 DDR DRAM, PBGA90 |
| 封装： | 13 X 8 MM, GREEN, PLASTIC, VFBGA-90 |
| 文件页数： | 94/95页 |
| 文件大小： | 3228K |
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Clock Change Frequency
One method of controlling the power efficiency in applications is to throttle the clock
that controls the device. The clock can be controlled by changing the clock frequency or
stopping the clock.
The device enables the clock to change frequency during operation only if all timing
parameters are met and all refresh requirements are satisfied.
The clock can be stopped altogether if there are no DRAM operations in progress that
would be affected by this change. Any DRAM operation already in process must be com-
pleted before entering clock stop mode; this includes the following timings: tRCD, tRP,
tRFC, tMRD, tWR, and tRPST. In addition, any READ or WRITE burst in progress must be
complete. (see READ Operation (page 59), and WRITE Operation (page 70).)
CKE must be held HIGH with CK = LOW and CK# = HIGH for the full duration of the
clock stop mode. One clock cycle and at least one NOP or DESELECT is required after
the clock is restarted before a valid command can be issued.
Figure 53: Clock Stop Mode
Exit clock stop mode
CKE
CK
CK#
Command
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NOP
Ta1
Ta2
Tb3
Tb4
Don’t Care
Address
DQ, DQS
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Enter clock stop mode
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CMD2
Valid
CMD2
Valid
NOP1
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All DRAM activities must be complete
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Notes: 1. Prior to Ta1, the device is in clock stop mode. To exit, at least one NOP is required be-
fore issuing any valid command.
2. Any valid command is supported; device is not in clock suspend mode.
Micron Confidential and Proprietary
Advance
512Mb: x16, x32 Mobile LPDDR SDRAM
Clock Change Frequency
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. B 2/10 EN
94
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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