![](http://datasheet.mmic.net.cn/170000/MT46H32M16LGBF-54LIT-C_datasheet_9466316/MT46H32M16LGBF-54LIT-C_48.png)
Figure 15: Initialize and Load Mode Registers
CKE
LVCMOS
HIGH LEVEL
DQ
BA0, BA1
Load standard
mode register
Load extended
mode register
tMRD4
tRFC4
Power-up: VDD and CK stable
T = 200s
High-Z
DM
DQS
High-Z
Address
Row
A10
Row
CK
CK#
VDD
VDDQ
tCH
tCL
tCK
Command1
LMR
NOP
LMR
tIS tIH
BA0 = L,
BA1 = L
BA0 = L,
BA1 = H
Op-code
tIS tIH
Op-code
PRE
All banks
T0
T1
Ta0
Tb0
Tc0
Td0
Te0
Tf0
Don’t Care
Bank
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tRP4
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NOP2
AR
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NOP3
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ACT3
Notes: 1. PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command; AR = AUTO RE-
FRESH command; ACT = ACTIVE command.
2. NOP or DESELECT commands are required for at least
200μs.
3. Other valid commands are possible.
4. NOPs or DESELECTs are required during this time.
Micron Confidential and Proprietary
Advance
512Mb: x16, x32 Mobile LPDDR SDRAM
Initialization
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. B 2/10 EN
48
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