参数资料
型号: SPMC16V1CPU20
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100
封装: TQFP-100
文件页数: 120/128页
文件大小: 571K
代理商: SPMC16V1CPU20
MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
91
4.7.2 Exception Stack Frame
During exception processing, the contents of the program counter and condition code register are
stacked at a location pointed to by SK : SP. Unless it is altered during exception processing, the stacked
PK : PC value is the address of the next instruction in the current instruction stream, plus $0006. Figure
16 shows the exception stack frame.
Figure 16 Exception Stack Frame Format
4.7.3 Exception Processing Sequence
Exception processing is performed in four phases.
A. Priority of all pending exceptions is evaluated, and the highest priority exception is processed
first.
B. Processor state is stacked, then the CCR PK extension field is cleared.
C. An exception vector number is acquired and converted to a vector address.
D. The content of the vector address is loaded into the PC, and the processor jumps to the excep-
tion handler routine.
Table 49 Exception Vector Table
Vector
Number
Vector
Address
Space
Type of
Exception
0
0000
P
Reset — Initial ZK, SK, and PK
0002
P
Reset — Initial PC
0004
P
Reset — Initial SP
0006
P
Reset — Initial IZ (Direct Page)
4
0008
D
Breakpoint
5
000A
D
Bus Error
6
000C
D
Software Interrupt
7
000E
D
Illegal Instruction
8
0010
D
Division by Zero
9 – E
0012 – 001C
D
Unassigned, Reserved
F
001E
D
Uninitialized Interrupt
10
0020
D
Unassigned, Reserved
11
0022
D
Level 1 Interrupt Autovector
12
0024
D
Level 2 Interrupt Autovector
13
0026
D
Level 3 Interrupt Autovector
14
0028
D
Level 4 Interrupt Autovector
15
002A
D
Level 5 Interrupt Autovector
16
002C
D
Level 6 Interrupt Autovector
17
002E
D
Level 7 Interrupt Autovector
18
0030
D
Spurious Interrupt
19 – 37
0032 – 006E
D
Unassigned, Reserved
38 – FF
0070 – 01FE
D
User-Defined Interrupts
High Address
SP After Exception Stacking
Condition Code Register
High Address
Program Counter
SP Before Exception Stacking
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