- 您现在的位置：买卖IC网 > PDF目录85254 > SPMC16V1CPU20 (MOTOROLA INC) 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 PDF资料下载
参数资料
| 型号： | SPMC16V1CPU20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 125/128页 |
| 文件大小： | 571K |
| 代理商： | SPMC16V1CPU20 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页当前第125页第126页第127页第128页
MOTOROLA
MC68HC16V1
96
MC68HC16V1TS/D
FRZ1 — FREEZE Assertion Response
0 = Ignore the FREEZE signal on the IMB
1 = Halt the QSPI (on a transfer boundary)
FRZ1 determines what action is taken by the QSPI when the FREEZE signal of the IMB is asserted.
FREEZE is asserted whenever the CPU enters the background mode.
FRZ0 — Not Implemented
Bits [12:8] — Not Implemented
SUPV — Supervisor/Unrestricted Data Space
This bit has no effect because the CPU16 always operates in the supervisor mode.
IARB[3:0] — Interrupt Arbitration Identification Number
The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority. Each
module that can generate interrupt requests must be assigned a unique, non-zero IARB field value.
QTEST — QSM Test Register
$YFFC02
QTEST is used during factory testing of the QSM.
QILR determines the priority level of interrupts requested by the QSM.
ILQSPI[2:0] — Interrupt Level for QSPI
ILQSPI determines the priority of QSPI interrupts. This field must be given a value between $0 (inter-
rupts disabled) to $7 (highest priority).
ILSCI[2:0] — Interrupt Level of SCI
ILSCI determines the priority of SCI interrupts. This field must be given a value between $0 (interrupts
disabled) to $7 (highest priority).
If ILQSPI and ILSCI are the same nonzero value, and both submodules simultaneously request inter-
rupt service, QSPI has priority.
At reset, QIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector in the excep-
tion table. This vector is selected until QIVR is written. A user-defined vector ($40–$FF) should be writ-
ten to QIVR during QSM initialization.
After initialization, QIVR determines which two vectors in the exception vector table are to be used for
QSM interrupts. The QSPI and SCI submodules have separate interrupt vectors adjacent to each other.
Both submodules use the same interrupt vector with the least significant bit (LSB) determined by the
submodule causing the interrupt.
QILR — QSM Interrupt Levels Register
$YFFC04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ILQSPI[2:0]
ILSCI[2:0]
QIVR
RESET:
0
QIVR — QSM Interrupt Vector Register
$YFFC05
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
QILR
INTV[7:0]
RESET:
0
1
相关PDF资料 |
PDF描述 |
|---|---|
| S1C60N05F0A0100 | MICROCONTROLLER, PQFP60 |
| SC3S12P128J0CLHR | 16-BIT, MROM, 1.05 MHz, MICROCONTROLLER, PQFP64 |
| SC3S12P128J0CLH | 16-BIT, MROM, 1.05 MHz, MICROCONTROLLER, PQFP64 |
| SC3S12P128J0CQKR | 16-BIT, MROM, 1.05 MHz, MICROCONTROLLER, PQFP80 |
| S908QY2AD1MDW | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SPMC387-01 | 制造商:SSDI 制造商全称:Solid States Devices, Inc 功能描述:50 WATT RADIATION HARDENED DC-DC POWER CONVERTER |
| SPMC68CK338CPV14 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:32-Bit Modular Microcontroller |
| SPMC802B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:32-pin General Purpose Microcontroller (OTP) |
| SPMC802B-C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:32-pin General Purpose Microcontroller (OTP) |
| SPMC802B-PD03 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:32-pin General Purpose Microcontroller (OTP) |
发布紧急采购，3分钟左右您将得到回复。