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参数资料
| 型号： | SPMC16V1CPU20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 44/128页 |
| 文件大小： | 571K |
| 代理商： | SPMC16V1CPU20 |
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MOTOROLA
MC68HC16V1
22
MC68HC16V1TS/D
When an externally generated reference signal (as opposed to a crystal) is applied through the EXTAL
pin, regardless of the clock mode chosen, the XTAL pin must be left floating.
3.3.3 Clock Synthesizer Operation
VDDSYN is used to power the clock circuits when the system clock is synthesized from a slow or fast
reference. A separate power source increases MCU noise immunity and can be used to run the clock
when the MCU is powered down. A quiet power supply must be used as the VDDSYN source. Adequate
external bypass capacitors should be placed as close as possible to the VDDSYN pin to assure stable
operating frequency. When an external system clock signal is applied and the PLL is disabled, VDDSYN
should be connected to the VSS supply.
A voltage controlled oscillator (VCO) in the PLL generates the system clock signal. To maintain a 50%
clock duty cycle, the internal VCO frequency is either two or four times the system clock frequency, de-
pending on the state of the X bit in SYNCR. The clock signal is fed back to a divider/counter. The divider
controls the frequency of one input to a phase comparator. The other phase comparator input is a ref-
erence signal, either from the crystal oscillator or from an external source. The comparator generates
a control signal proportional to the difference in phase between the two inputs. This signal is routed
through a low-pass filter and used to correct VCO output frequency.
Filter circuit implementation can vary, depending upon the external environment, reference multiplica-
tion factor, and required clock stability. Figure 7 shows two recommended system clock filter networks
for slow and fast reference modes. XFC pin leakage must be kept as low as possible to maintain opti-
mum stability and PLL performance.
An external filter network connected to the XFC pin is not required when an external system clock signal
is applied and the PLL is disabled (VDDSYN = 0). The XFC pin must be left floating in this case.
Figure 7 System Clock Filter Networks
The synthesizer locks when the divided VCO frequency is equal to fref. Lock time is affected by the filter
time constant and by the amount of difference between the two comparator inputs. Whenever a com-
parator input changes, the synthesizer must relock. Lock status is shown by the SLOCK bit in SYNCR.
During power-up, the MCU does not come out of reset until the synthesizer locks. Crystal type, charac-
teristic frequency, and layout of external oscillator circuitry affect lock time.
The reset clock configuration involving VDDSYN and PCON0 determines the clock mode selected. The
functionality of SYNCR is affected by these configuration options.
MAINTAIN LOW LEAKAGE ON THE XFC NODE.
VDDSYN
XFC
VSSSYN
18 k
C3
C4
3300 pF
C1
C2
R1
16/32 XFC CONN
VDDSYN
0.01
F
0.1
F
XFC *
VSSSYN
1000 pF 20 k
C3
C4
100 pF
C1
C2
R1
FAST REFERENCE
SLOW REFERENCE
*
0.1
F
0.01
F
0.1
F
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