- 您现在的位置：买卖IC网 > PDF目录85254 > SPMC16V1CPU20 (MOTOROLA INC) 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 PDF资料下载
参数资料
| 型号： | SPMC16V1CPU20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 53/128页 |
| 文件大小： | 571K |
| 代理商： | SPMC16V1CPU20 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页当前第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页
MOTOROLA
MC68HC16V1
30
MC68HC16V1TS/D
After reset, bus monitor timeout value defaults to 64 system clocks.
NOTE
For external accesses, this time-out value should be longer than the chip-select
access time.
3.4.1 Bus Monitor
The internal bus monitor checks for excessively long response times during normal bus cycles
(DTACK). The monitor asserts the internal BERR signal if response time is excessive.
DTACK response time is measured in clock cycles. The maximum allowable response time can be se-
lected by setting BMT[1:0].
The BME bit in SYPCR enables the internal bus monitor for internal to external bus cycles. The monitor
does not check DTACK response on the external bus unless the CPU16 initiates the bus cycle. If a sys-
tem contains external bus masters, an external bus monitor must be implemented and the internal to
external bus monitor option must be disabled.
3.4.2 Spurious Interrupt Monitor
The spurious interrupt monitor issues internal BERR if no interrupt arbitration occurs during an IACK
cycle. Leaving IARB[3:0] set to %0000 in the module configuration register of any peripheral that can
generate interrupts will cause a spurious interrupt. Refer to Table 49 for the CPU16 interrupt vector ta-
ble.
3.4.3 Halt Monitor
The halt monitor responds to an assertion of the HALT signal on the internal bus caused by a double
bus fault. This signal is asserted by the CPU16 after a double bus fault occurs. If the HME bit is set to
one, the halt monitor is enabled, and asserts RESET when the HALT signal is asserted. A flag in the
reset status register (RSR) indicates that the last reset was caused by the halt monitor. The halt monitor
reset can be inhibited by clearing the HME bit in SYPCR.
3.4.4 Timer Control
The timer control register selects the time base for the real-time clock and software watchdog. It also
sets the vector used when these timers generate interrupts.
Table 13 Bus Monitor Timeout Period
BMT[1:0]
Timeout
0 0
64 System Clocks
0 1
32 System Clocks
1 0
16 System Clocks
1 1
8 System Clocks
TIC — Timer Control Register
$YFFA52
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PRR
SWC[2:0]
0
RTC[2:0]
TIV[7:0]
RESET:
0
相关PDF资料 |
PDF描述 |
|---|---|
| S1C60N05F0A0100 | MICROCONTROLLER, PQFP60 |
| SC3S12P128J0CLHR | 16-BIT, MROM, 1.05 MHz, MICROCONTROLLER, PQFP64 |
| SC3S12P128J0CLH | 16-BIT, MROM, 1.05 MHz, MICROCONTROLLER, PQFP64 |
| SC3S12P128J0CQKR | 16-BIT, MROM, 1.05 MHz, MICROCONTROLLER, PQFP80 |
| S908QY2AD1MDW | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SPMC387-01 | 制造商:SSDI 制造商全称:Solid States Devices, Inc 功能描述:50 WATT RADIATION HARDENED DC-DC POWER CONVERTER |
| SPMC68CK338CPV14 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:32-Bit Modular Microcontroller |
| SPMC802B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:32-pin General Purpose Microcontroller (OTP) |
| SPMC802B-C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:32-pin General Purpose Microcontroller (OTP) |
| SPMC802B-PD03 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:32-pin General Purpose Microcontroller (OTP) |
发布紧急采购，3分钟左右您将得到回复。