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参数资料
| 型号： | SPMC16V1CPU20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 68/128页 |
| 文件大小： | 571K |
| 代理商： | SPMC16V1CPU20 |
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MOTOROLA
MC68HC16V1
44
MC68HC16V1TS/D
3.6.2.7 DTACK Operation
The default operation of DTACK/PD4 can be overridden by driving the ADDR8/DATA8 pin to the states
shown in Table 28.
3.6.2.8 CPU Function Code Operation
The default operation of FC[2:0]/PE[7:5] can be overridden by driving the ADDR9/DATA9 pin to the
states shown in Table 29.
3.6.2.9 CLKOUT Operation
The default operation of CLKOUT/PE4 can be overridden by driving the ADDR0/DATA0 pin to the
states shown in Table 30.
3.6.3 MCU Module Pin Function During Reset
Generally, module pins default to port functions, and input/output ports are set to input state. This is
accomplished by disabling pin functions in the appropriate control registers, and by clearing the appro-
priate port data direction registers. Refer to individual module sections in this manual for more informa-
tion.
3.6.4 Reset Timing
The RESET input must be asserted for a specified minimum period for reset to occur. External RESET
assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor
time-out period) in order to protect write cycles from being aborted by reset. While RESET is asserted,
SLIM pins are either in an inactive, high-impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic clocks the signal into
an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after
it detects that the RESET signal is no longer being externally driven, to guarantee this length of reset
to the entire system.
If an internal source asserts a reset signal, the reset control logic asserts RESET for a minimum of 512
cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert
RESET until the internal reset signal is negated.
Table 28 DTACK/PD4 Default Configuration Override
Shadow Bit
ADDR8/DATA8
Pin Configuration
PCON4
0
PD4
1DTACK
Table 29 FC[2:0]/PE[7:5] Default Configuration Override
Shadow Bit
ADDR9/DATA9
Pin Configuration
PCON3
0
PE[7:5]
1
FC[2:0]
Table 30 CLKOUT/PE4 Default Configuration Override
Shadow Bit
ADDR0/DATA0
Pin Configuration
PCON1
0
PE4
1
CLKOUT
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