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参数资料
| 型号： | SPMC16V1CPU20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 87/128页 |
| 文件大小： | 571K |
| 代理商： | SPMC16V1CPU20 |
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MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
61
3.9.3 Chip-Select Control Register
The chip select control register contains bits controlling the size of accesses made by each of the chip
selects, the response to IACK cycles when not programming a chip select to match the cycle, and the
option to re-program the R/W and DS pins as alternate read and write strobes.
IPL[7:1] — Interrupt Priority Level
Setting any of the bits in this field to one determines whether or not CSA responds to IACK cycles of
the corresponding interrupt level. If all bits in IPL[7:1] remain cleared to zero, CSA does not respond to
IACK cycles. If one or more of these bits is set to one, CSA responds according to the IACK bit and the
options programmed for CSA.
IACK — Interrupt Acknowledge Response
This bit, along with the IACK/CS bit in CSORA, determines CSA response to an IACK cycle. The re-
sponse, based on the programming of these two bits, is summarized in Table 39.
MUX[A:C] — Non-Multiplexed Bus Override
These three bits allow multiplexed bus cycles to occur on a non-multiplexed external bus on a per chip-
select basis. If a match occurs in a chip-select option and base address register pair, and the MUX bit
for the corresponding chip-select is set to one, the access to that block of memory is done using multi-
plexed address and data.
NOTE
When the SLIM is configured at reset for multiplexed bus operation, these bits have
no meaning and are ignored.
ADRDIS — Address Bus Disable
This bit disables the external address bus during internal accesses. When set, the external address bus
is not driven on internal cycles unless the show cycle feature is being used. Disabling the address bus
results in the addition of one wait state for all cycles, internal and external.
0 = Enable external address bus during internal accesses.
1 = Disable external address bus during internal accesses.
1. Can also be terminated by DTACK pin (if available).
CSCR — Chip-Select Control Register
$YFFA6C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IPL7
IPL6
IPL5
IPL4
IPL3
IPL2
IPL1
IACK
MUXA
MUXB
MUXC
ADRDIS
SIZA
SIZB
SIZC
RWEN
RESET:
0
PCON9
PCON7
PCON5
0
Table 39 IACK Cycle Response To External IRQ Input Assertion
IACK Cycle Conditions
Response
IRQ Pin
Asserted
State of IPL Bit
in CSCR
Corresponding
to IRQ Level
State of IACK
Bit in CSCR
State of
IACK/CS Bit
in CSORA
IACK Cycle
Termination
AS
CSA
Source of
Vector
N
—
Internal bus error
1
None
Y
0
None/Bus Monitor/
Internal bus error
1
None
Y
1
0
Internal Autovector
1
Correspond-
ing Autovector
Y
—
0
1
External DTACK
0
1
External
Y—
1
0
Internal DTACK1
0
1
External
Y—
1
Internal DTACK1
0
External
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