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参数资料
| 型号： | SPMC16V1CPU20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 86/128页 |
| 文件大小： | 571K |
| 代理商： | SPMC16V1CPU20 |
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MOTOROLA
MC68HC16V1
60
MC68HC16V1TS/D
3.9.1 Programmable Chip-Select Circuit
Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write
strobes, or interrupt acknowledge signals. Logic can also generate DTACK signals internally. A single
DTACK generator is shared by all circuits. Multiple chip selects assigned to the same block of addresses
must have the same number of wait states.
Blocks of addresses are assigned to each chip-select function with sizes of 2 Kbytes to 1 Mbyte. They
can be selected by writing values to the appropriate base address register (CSBAR). However, because
the logic state of ADDR20 always follows that of ADDR19 on the CPU16, the largest usable block size
is 512 Kbytes. Address blocks for separate select functions can overlap.
NOTE
The largest practical block size on the MC68HC16V1 is 256 Kbytes because the
ADDR[23:18] pins are not bonded.
When a memory access occurs, chip-select logic compares address space type, address, type of ac-
cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in
the chip-select registers. If all parameters match, the appropriate chip-select signal is asserted. Select
signals are active low.
If a chip-select function is given the same address as a microcontroller module, an access to that ad-
dress goes to the module, and the chip-select signal is not asserted.
3.9.2 Chip-Select Pin Assignment
Each chip-select pin can have two or more functions. Chip-select configuration out of reset is deter-
mined by operating mode. In all expanded modes, the boot ROM select signal (CSB) is automatically
asserted out of reset if the SLIM boot ROM is disabled. In single-chip mode, all chip select pins are con-
figured as PD[7:5].The data bus size is controlled by the port size programmed in the chip-select control
register (CSCR). If CSA, CSB, and CSC are all programmed to 8-bit size, DATA[7:0] becomes port H
and DATA[15:8] are used as the 8-bit data bus. If any chip-select is configured with a 16-bit port size,
DATA[15:0] are configured as the 16-bit data bus and port H is not available.
NOTE
In expanded mode, the port sizes in the chip-selects must be programmed to de-
termine the data bus size, whether or not chip-select pins are available or are being
used.
Three independent bits in CSCR determine the port size for each chip select as 8 or 16 bits. Three other
bits in the port D pin assignment register (PDPAR) determine if each chip-select is used as digital I/O
or as a chip-select (refer to Table 38). The state of these bits at reset is determined by the correspond-
ing mask-programmed shadow bits in the port/clock configuration shadow register (PCON). Default re-
set values for some bits in the shadow register can be overridden by the state of specific pins during
reset. Refer to 3.6.2 Default Configuration Override During Reset for more information.
Table 38 Chip-Select Pin Assignment Encoding
Chip-Select
PDPAR Bit
PDPAR
Shadow Bit
Pin Function
CSCR Bit
CSCR
Shadow Bit
Port Size
CSA
PDPAR7
PCON10
0 = PD7
1 = CSA
SIZA
PCON9
0 = 8 Bit
1 = 16 Bit
CSB
PDPAR6
PCON8
0 = PD6
1 = CSB
SIZB
PCON7
CSC
PDPAR5
PCON6
0 = PD5
1 = CSC
SIZC
PCON5
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