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参数资料
| 型号： | SPMC16V1CPU20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 71/128页 |
| 文件大小： | 571K |
| 代理商： | SPMC16V1CPU20 |
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MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
47
3.7.1 Interrupt Acknowledge Cycle
Interrupt acknowledge bus cycles are generated during exception processing. When the CPU16 de-
tects one or more interrupt requests of a priority higher than the interrupt priority mask value, it performs
a CPU space read from address $FFFFF : [IP] : 1.
The CPU space read cycle performs two functions: it places a mask value corresponding to the highest
priority interrupt request on the address bus, and it acquires an exception vector number from the inter-
rupt source. The mask value also serves two purposes: it is latched into the CCR IP field in order to
mask lower-priority interrupts during exception processing, and it is decoded by modules that have re-
quested interrupt service to determine whether the current interrupt acknowledge cycle pertains to
them.
Modules that have requested interrupt service decode the IP value placed on the address bus at the
beginning of the interrupt acknowledge cycle, and if their requests are at the specified IP level, respond
to the cycle. Arbitration between simultaneous requests of the same priority is performed by means of
serial contention between module interrupt arbitration (IARB) field values.
Each module that can make an interrupt service request, including the SLIM, has an IARB field in its
module configuration register. An IARB field can be assigned a value from %0001 (lowest priority) to
%1111 (highest priority). A value of %0000 in an IARB field causes the CPU16 to process a spurious
interrupt exception when an interrupt from that module is recognized.
Because the EBI manages external interrupt requests, the SLIM IARB value is used for arbitration be-
tween internal and external interrupt requests. The reset value of IARB for the SLIM is %1111, and the
reset IARB value for all other modules is %0000. Initialization software must assign different IARB val-
ues to implement an arbitration scheme.
Each module must have a unique IARB value. When two or more IARB fields have the same non-zero
value, the CPU16 interprets multiple vector numbers simultaneously, with unpredictable consequences.
Arbitration must always take place, even when a single source requests service. This point is important
for two reasons: the CPU interrupt acknowledge cycle is not driven on the external bus unless the SLIM
wins contention, and failure to contend causes an interrupt acknowledge bus cycle to be terminated by
a bus error, which causes a spurious interrupt exception to be taken.
When arbitration is complete, the dominant module must place an interrupt vector number on the data
bus and terminate the bus cycle. In the case of an external interrupt request, because the interrupt ac-
knowledge cycle is transferred to the external bus, an external device must decode the mask value and
respond with a vector number, then generate bus cycle termination signals. If the device does not re-
spond in time, a spurious interrupt exception is taken.
3.7.2 Interrupt Processing Summary
A summary of the interrupt processing sequence follows. When the sequence begins, a valid interrupt
service request has been detected and is pending.
A. The CPU finishes higher priority exception processing or reaches an instruction boundary.
B. Processor state is stacked, then the CCR PK extension field is cleared.
C. The interrupt acknowledge cycle begins:
1.
FC[2:0] are driven to %111 (CPU space) encoding.
2.
The address bus is driven as follows. ADDR[23:20] = %1111; ADDR[19:16] = %1111,
which indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4]
= %111111111111; ADDR[3:1] = the priority of the interrupt request being acknowledged;
and ADDR0 = %1.
3.
Request priority is latched into the CCR IP field from the address bus.
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