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参数资料
| 型号： | SPMC16V1CPU20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 46/128页 |
| 文件大小： | 571K |
| 代理商： | SPMC16V1CPU20 |
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MOTOROLA
MC68HC16V1
24
MC68HC16V1TS/D
3.3.4 Clock Control
The clock control circuits determine system clock frequency and clock operation under special circum-
stances, such as following loss of synthesizer reference or during low-power operation. Clock source is
determined by the logic state of the two shadow bits in the port/clock configuration register (PCON2 and
PCON0) and VDDSYN pin during reset.
The synthesizer control register (SYNCR) can be read or written at any time. The encoding and default
value of the upper byte of SYNCR depend on the clock mode selected at reset.
For slow reference mode, the default value is $3F, which corresponds to an operating frequency of 256
times fref. For a 32.768 kHz crystal, the operating frequency is 8.388 MHz.
In fast reference mode, with PCON2 cleared to zero, the default value of the upper byte is $80, which
corresponds to a 1-to-1 match of the reference frequency. With PCON2 set to one, the default value of
the upper byte is $30, which corresponds to an operating frequency of two times fref. For a 4.194 MHz
crystal, the operating frequency is 8.388 MHz.
In external clock mode, the default value of the upper byte is $80, which corresponds to an operating
frequency which is equal to the input frequency on EXTAL. Strict minimum duty cycle requirements ap-
ply. Refer to 3.3.2 Clock Modes for more information. The default value is forced into the SYNCR upon
reset, along with the default values of the other bits in the register.
X — Frequency Control Bit
This bit controls a one-bit divider which drives the system clock in all modes. When X is set, the divider
is bypassed; when clear, the system clock is divided by two.
SYNCR — Synthesizer Control Register
$YFFA04
Slow Reference Mode
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
W
Y[5:0]
EDIV
STOSC LOSCD
SLIMP
SLOCK RSTEN
STSLIM
STEXT
RESET:
0
1
0
1
0
Fast Reference Mode
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
W[2:0]
RSVD
Y[2:0]
EDIV
STOSC LOSCD
SLIMP
SLOCK RSTEN
STSLIM
STEXT
RESET:
PCON2
0
PCON2 PCON2
0
1
0
External Clock Mode
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
RSVD
Y[2:0]
EDIV
STOSC LOSCD
SLIMP
SLOCK RSTEN
STSLIM
STEXT
RESET:
1
0
1
0
1
0
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