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参数资料
| 型号： | SPMC16V1CPU20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 36/128页 |
| 文件大小： | 571K |
| 代理商： | SPMC16V1CPU20 |
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MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
15
The module configuration register (SLIMCR) controls system configuration. The reset state of some of
the bits in SLIMCR depend on the state of corresponding bits in the module configuration shadow reg-
ister (MCRC).
LOAD — Pad Driver Load
This bit controls the drive strength of all pad output drivers by selecting whether one or two pad drivers
are enabled. This bit cannot be written and is controlled by the state of MCRC15.
0 = One pad driver is enabled.
1 = Two pad drivers are enabled.
FRZ[1:0] — FREEZE Assertion Response
Table 8 shows the effects of the assertion of FREEZE on the software watchdog, the real-time clock,
and the prescaler. These bits can be written at any time.
MODE[2:0] — Mode Configuration
These bits control the operating mode configuration of the external address and data bus, as shown in
Table 9. These bits cannot be written and are controlled during reset by MCRC[11:9] if DCRD = 1, or
by DS, SIZE, and R/W if DRCD = 0.
SHEN — Show Cycles Enable
This bit determines whether or not the EBI drives the data bus and the AS, DS, and R/W control signals
during internal transfer operations.
NOTE
The address bus is always driven during internal cycles unless the ADRDIS bit is
set to one in the chip-select control register (CSCR). This bit can be written at any
time.
0 = Show cycles disabled
1 = Show cycles enabled. Data bus, AS, DS, and R/W control signals are driven during internal
transfer operations.
SUPV — Supervisor/Unrestricted Data Space
The MC68HC16V1 operates only in supervisor mode. SUPV has no effect.
Table 8 Effects of FREEZE Assertion
FRZ[1:0]
Disabled Elements
0
None
0
1
Bus monitor
1
0
Software watchdog, real-time clock, prescaler
1
Both
Table 9 Mode Configuration Bit Field
MODE[2:0]
Configuration
0
X
Reserved
1
0
Expanded non-multiplexed mode
1
0
1
Expanded multiplexed mode
1
X
Single-chip mode
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