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参数资料
| 型号： | SPMC16V1CPU20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 42/128页 |
| 文件大小： | 571K |
| 代理商： | SPMC16V1CPU20 |
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MOTOROLA
MC68HC16V1
20
MC68HC16V1TS/D
When VDDSYN is held high during reset, the clock synthesizer generates a clock signal from either a
crystal oscillator or an external reference input. The clock synthesizer control register (SYNCR) deter-
mines operating frequency and various clock options. When VDDSYN is held low during reset, the clock
synthesizer is disabled, and an external system clock signal must be applied.
3.3.2 Clock Modes
In slow reference mode, the system clock is generated on-chip by a phase locked loop (PLL) frequency
synthesizer and from an external reference (fref) that is typically 32.768 kHz. The frequency of the sys-
tem clock is controlled by programming the X, Y, and W bits in the SYNCR.
NOTE
In slow reference mode, the fref input rate is not restricted to a single value (typically
32.768 kHz), but can range from 25 kHz to 50 kHz.
To generate the system clock using a slow reference, a crystal must be connected between the EXTAL
and XTAL pins. Figure 5 shows a typical circuit.
1. In external clock mode, the state of PCON0 has no effect on clock operation.
2. The default reset state mask-programmed in the PCON0 shadow bit can be overridden by the state of the
FREEZE pin during reset when the DRCD pin is held low.
3. The default reset state mask-programmed in the PCON2 shadow bit can be overridden by the state of the IRQX
pin during reset, if the DRCD pin is held low.
Table 11 Clock Sources
MODE
SYNCR X/W/Y Bit
Assignments
X/W/Y Reset Val-
ues
Clock Equation
External Clock
X
Y[2:0]
X = 1
Y = 0
VDDSYN = 0
PCON0 = X1
Fast Reference
X
W[2:0]
Y[2:0]
PCON2 = 02
VDDSYN = 1
PCON0 = 0
X = 1
W = 0
Y = 0
PCON2 = 13
X = 0
W = 3
Y = 0
Slow Reference
X
W
Y[5:0]
X = 0
W = 0
Y = 63
VDDSYN = 1
PCON0 = 1
f
sys
f
ref
2X
–
() 2
Y
()
-----------------------------
, for Y
6
≤
=
f
sys
f
ref W1
+
()
2X
–
() 2
Y
()
-----------------------------
, for Y
6
≤
=
f
sys
4f
ref Y1
+
() 2
2W
X
+
()
=
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