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参数资料
| 型号： | SPMC16V1CPU20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 58/128页 |
| 文件大小： | 571K |
| 代理商： | SPMC16V1CPU20 |
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MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
35
When the real-time clock downcounter (RTDC) reaches zero, the RZ flag in the SYPCR is set to one.
An interrupt is generated if the TIEN bit is set and if TIQL[2:0] is non-zero. RTDC then loads the current
RTP value and begins counting again. When RESET is asserted, RTDC is not affected.
3.4.7 Real-Time Clock and Software Watchdog in Chained Mode
The real-time clock and the software watchdog can be chained together to form a 32-bit downcounter.
At this time, SWDC acts as the most significant word (MSW) and RTDC acts as the least significant
word (LSW). Upon reaching zero, the least significant word, rather than reloading the period register,
counts the SWDC down by one as it rolls over to $FFFF, and then continues counting.
One 32-bit or two 16-bit values can be written to the SWP and RTP registers to trigger the downcounter
chain.
NOTE
The downcounter chain does not begin counting until the lower byte of RTP is writ-
ten.
The counter can be read at any time. Anything other than 32-bit reads, however, may not be accurate.
The concatenated SWP/RTP count value is determined by the following equation:
1. Refer to Table 17 for chained timer time-out period information.
2. These frequency categories are frequencies which are output from the clock select mux to the prescaler. The
prescaler frequency is defined as fpre = fsys/2 if PCLK = 0 or fpre = fref/2 if PCLK = 1. Refer to Figure 9.
Table 16 Real-Time Period Ranges (Timers Not Chained)1
RTC[2:0] Clock
Control Settings
Clock
Source
Time-Out Ranges for Typical Values of fref and fsys
2
32.768 kHz
4.194 MHz
16.777 MHz
20.972 MHz
000
fsys/2
61.0
s to
4.0 s
477 ns to
31.3 ms
119 ns to
7.81 ms
95.4 ns to
6.25 ms
001
fref/2
61.0
s to
4.0 s
477 ns to
31.3 ms
119 ns to
7.81 ms
95.4 ns to
6.25 ms
010
fpre/1024
62.5 ms to
68.3 mins
488
s to
32 s
122
s to
8 s
97.7
s to
6.4 s
011
fpre/256
15.6 ms to
17.1 mins
122
s to
8 s
30.5
s to
2 s
24.4
s to
1.6 s
100
fpre/64
3.91 ms to
4.27 mins
30.5
s to
2 s
7.63
s to
500 ms
6.10
s to
400 ms
101
fpre/16
977
s to
64.0 s
7.63
s to
500 ms
1.91
s to
125 ms
1.53
s to
100 ms
1
0
Real-Time Clock Off
—
1
Real-Time Clock Off
—
RTDC — Real-Time Clock Downcounter
$YFFA5E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POWER-ON RESET ONLY:
0
Concatenated SWP/RTP Count Value
Desired Period of Chained Timer
RTC Clock Source
×
=
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