
MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
21
Figure 5 Slow Reference Crystal Circuit
In fast reference mode, the system clock is generated by the PLL from an external reference (fref) which
is typically 4.194 MHz. The system clock frequency at reset is determined by the PCON2 shadow bit.
Fast reference mode reduces jitter over the slow reference mode and, like slow reference mode, pro-
vides a 50% duty cycle system clock regardless of the reference duty cycle.
NOTE
In fast reference mode, the fref input rate is not restricted to a single value (typically
4.194 MHz), but can range from 1 MHz to 6 MHz.
To generate the system clock using a fast reference, a crystal must be connected between the EXTAL
and XTAL pins. Figure 6 shows a typical circuit.
Figure 6 Fast Reference Crystal Circuit
In external clock mode (when a crystal is not used), the clock source must be driven onto the EXTAL
pin. This clock is used to generate the system clock directly (the PLL is turned off). At reset, the system
clock frequency is the same as the input clock frequency (fref) and no dividers are present. If this fre-
quency is the same as the maximum specified system clock frequency, it must not violate strict mini-
mum duty cycle requirements. The duty cycle of the input is critical, especially at near maximum
operating frequencies.
The relationship between clock signal duty cycle and clock signal period is expressed as follows:
16 OSCILLATOR
EXTAL
XTAL
10 M
330 k
22 pF*
VSSI
RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A KDS (DAISHINKU) DMX-38 32.768 kHz CRYSTAL.
SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT.
*
R1
C1
C2
R2
16 OSCILLATOR 4M
EXTAL
XTAL
1 M
1.5 k
27 pF*
VSSI
RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A KDS041-18 4.194 MHz CRYSTAL.
SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT.
*
R1
C1
C2
R2
Minimum External Clock Period
Minimum External Clock High/Low Time
50 %
Percentage Variation of External Clock Input Duty Cycle
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