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参数资料
| 型号： | SPMC16V1CPU20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 40/128页 |
| 文件大小： | 571K |
| 代理商： | SPMC16V1CPU20 |
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MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
19
PCON2 — 2X/1X System Clock
This bit controls the W and X bit reset states when the SLIM is reset in fast reference mode.
0 = System clock frequency is the same as the reference frequency.
1 = System clock frequency is twice the reference frequency.
This bit can be overridden by driving IRQX to the desired state if DRCD is low during reset.
PCON1 — Port E4 Default Configuration
This bit contains the default reset value for the CLKOUT/PE4 pin assignment bit in the port E pin as-
signment register (PEPAR). This allows the pin to come out of reset as CLKOUT or digital I/O.
PCON0 — Clock Select
This bit, along with VDDSYN = VDD, selects the clock source as either fast or slow reference.
0 = Clock source is fast reference
1 = Clock source is slow reference
If VDDSYN = VSS, the clock source is external, regardless of the state of this bit. This bit can be overrid-
den by driving FREEZE to the desired state if DRCD is low during reset.
BOOT ROM — Reset and Interrupt Vector Configuration
$000000 – $0001FF
The boot ROM submodule in the SLIM provides the system with a small amount of mask programmable
memory used for initialization. The boot ROM submodule occupies 512 bytes (256 by 16 bits) of the
system memory and is accessible by byte or word. The ROMEN and ROMSU bits in SLIMCR control
access to the boot ROM. The contents of the boot ROM are user specified. The boot ROM on generic
devices will be filled with all $FF or all $00. Consult the factory for information on ordering devices with
a customer specified boot ROM.
3.3 System Clock
The system clock in the SLIM provides timing signals for the IMB modules and for the external bus in-
terface. Because the MCU is a fully static design, register and memory contents are not affected when
the clock rate changes. System hardware and software support changes in clock rate during operation.
3.3.1 System Clock Sources
The system clock signal can be generated from one of three sources. An internal phase-locked loop
(PLL) can synthesize the clock from a slow or fast reference, or the clock signal can be input from an
external frequency source. The slow reference typically is a 32.768 kHz crystal; the fast reference is
typically a 4.194 MHz crystal. The slow and fast references may be generated by sources other than a
crystal. Keep these clock sources in mind while reading the rest of this section.
The source of the system clock is determined at reset by the state of two shadow bits in the port/clock
sources.
The parameter “fref” refers to the frequency of the clock source connected to the EXTAL pin. Refer to
3.3.2 Clock Modes for more information.
The parameter “fsys” refers to the operating frequency of the MCU and has a defined relationship to fref
that depends on the clock operating mode selected during reset.
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