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参数资料
| 型号： | SPMC16V1CPU20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 72/128页 |
| 文件大小： | 571K |
| 代理商： | SPMC16V1CPU20 |
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MOTOROLA
MC68HC16V1
48
MC68HC16V1TS/D
D. Modules or external peripherals that have requested interrupt service decode the priority value
on ADDR[3:1]. If request priority is the same as the priority value in the address, IARB conten-
tion takes place. When there is no contention, the spurious interrupt monitor asserts BERR, and
a spurious interrupt exception is processed.
E. After arbitration, the interrupt acknowledge cycle can be completed in one of three ways:
1.
The dominant interrupt source supplies a vector number and DTACK to terminate the bus
cycle. The CPU16 acquires the vector number.
2.
The internal AVEC signal is asserted by the dominant interrupt source and the CPU16 gen-
erates an autovector number corresponding to interrupt priority.
3.
The bus monitor asserts BERR and the CPU16 generates the spurious interrupt vector
number.
F. The vector number is converted to a vector address.
G. The content of the vector address is loaded into the PC, and the processor transfers control to
the exception handler routine.
3.8 General-Purpose Input/Output
Most of the pins associated with the SLIM can be used for several different functions. Their primary
function is to provide an external bus interface for applications that require access to off-chip resources.
When not being used for their primary functions, these pins can be used as digital I/O pins. To facilitate
I/O functions, the SLIM pins are grouped into 8-bit ports. Each port has associated registers that are
used to configure the pins for the desired functions.
The SLIM contains eight general-purpose input/output ports: A, B, C, D, E, F, G, and H. All are available
as either input or output. All ports have two associated data registers used to monitor or control the state
of its pins.
The port output data register is readable and writable. Writes to the port output data registers cause IMB
data to be latched, which is then driven to the pads of all pins programmed as outputs. Reads of the
output data returns the current state of the data latch for all pins, regardless of the actual state of the
output pin.
The pin data registers return the current state of all pins regardless of whether they are input or output.
After reset, all pin data registers reflect the actual state of the pin, as reset causes all pins to become
inputs by clearing the data direction registers.
Ports C, D, E, and F have pin assignment registers that show if individual pins are configured for digital
I/O, or some other function. Ports A, B, and G do not have pin assignment registers and are configured
as digital I/O based on the mode of the SLIM as configured during reset. Port H does not have a pin
assignment register and is configured as digital I/O based on the mode of the SLIM and the program-
ming of the data port size bits of the chip selects (CSA, CSB, and CSC).
All ports have an associated data direction register that is used to configure port pins as either outputs
or inputs. In addition to the output data and pin data registers, port F has an edge-detect flag register
that indicates whether a transition has occurred on any of its pins.
Table 31 shows the primary functions of the general-purpose I/O ports and the modes in which the I/O
ports are available. “X” indicates port availability in a particular mode.
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