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参数资料
| 型号： | SPMC16V1CPU20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 37/128页 |
| 文件大小： | 571K |
| 代理商： | SPMC16V1CPU20 |
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MOTOROLA
MC68HC16V1
16
MC68HC16V1TS/D
MM — Module Mapping
0 = Internal modules are addressed from $7FF000 – $7FFFFF.
1 = Internal modules are addressed from $FFF000 – $FFFFFF.
IMB address lines ADDR[23:20] follow the logic state of ADDR19. MM corresponds to IMB ADDR23. If
it is cleared, the SLIM maps IMB modules into address space $7FF000 – $7FFFFF, which is inacces-
sible to the CPU. Modules remain inaccessible until reset occurs. MM can only be written once after
reset. Initialization software should leave MM set to logic level 1.
ROMSU — ROM Supervisor/Unrestricted Mode
The MC68HC16V1 operates only in supervisor mode. ROMSU has no effect.
ROMEN — ROM Enable
Allows boot ROM to respond to the 512-byte address range following $000000.
0 = Boot ROM does not respond and allows another internal module or external device to be
mapped starting at address $000000. After reset, ROMEN = 0 also enables CSB.
1 = Boot ROM responds to lower-order addresses.
IARB[3:0] — Interrupt Arbitration Field
Each module that can generate interrupt requests has an interrupt arbitration (IARB) field. Arbitration
between interrupt requests of the same priority is performed by serial contention between IARB field bit
values. Contention must take place whenever an interrupt request is acknowledged, even when there
is only a single pending request.
An IARB field must have a non-zero value for contention to take place. If an interrupt request from a
module with an IARB field value of %0000 is recognized, the CPU16 processes a spurious interrupt ex-
ception.
Because the SLIM routes external interrupt requests to the CPU16, the SLIM IARB field value is used
for arbitration between internal and external interrupts of the same priority. The reset value of IARB for
the SLIM is %1111 (highest priority), and the reset IARB value for all other modules is %0000, which
prevents SLIM interrupts from being discarded during initialization. These bits can be written at any
time.
The module configuration shadow register (MCRC) is a mask programmable register which contains
the default reset values of corresponding bits in SLIMCR. During reset, SLIMCR is loaded from this reg-
ister unless the drive reset configuration data (DRCD) pin is asserted. If DRCD is asserted during reset,
some MCRC shadow bits are overridden by the state of certain SLIM pins during reset. Refer to Table
1 for the factory specified MCRC value appropriate to the MCU package being used.
1. This bit is reserved for future use.
MCRC — Module Configuration Shadow Register
$YFFA0A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LOAD
0
RSVD1
MODE[2:0]
0
SUPV
MM
ROMSU ROMEN
IARB[3:0]
RESET:
USER SPECIFIED
SMD — Sub-Module Disable Register
$YFFA0D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UNUSED
BRKEN
CHIP
SELECT
TEST
SYS
PROT
RESET:
0
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