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参数资料
| 型号： | SPMC16V1CPU20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 54/128页 |
| 文件大小： | 571K |
| 代理商： | SPMC16V1CPU20 |
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MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
31
The timer control register selects the clock input to the software watchdog downcounter and the real-
time clock downcounter.
PRR — Prescaler Reset
Writing TIC with PRR set to one resets the prescaler (PRE) when changing the time base for the soft-
ware watchdog and/or the real-time clock.
0 = Prevents prescaler reset
1 = Permits prescaler reset
SWC[2:0] — Software Watchdog Clock Control
The SWC[2:0] field provides seven possible settings for choosing the input clock for the software watch-
dog downcounter. Refer to Table 14.
RTC[2:0] — Real-Time Clock Control
The RTC[2:0] field provides six possible settings for choosing the input clock for the real-time clock
downcounter. Refer to Table 14.
In the case of the SWC[2:0] field, the RTC extension setting allows the real-time downcounter and the
software watchdog downcounter to operate in chained mode (refer to paragraph 3.4.7 Real-Time Clock
and Software Watchdog in Chained Mode for more information).
The system clock and the crystal reference settings allow clocking the SWDOG and/or the RTC down-
counter by the crystal frequency divided by two, or the system clock divided by two, respectively. The
prescaler settings, on the other hand, allow one of four prescaler taps to clock the downcounters.
The prescaler frequency (fpre) is defined as follows based on the setting of the PCLK bit in SYPCR:
or
Resetting out of LPSTOP has no effect on either the SWC or RTC fields. In this way, the SWDOG and
the RTC continue to run with the same clock configuration both in and out of LPSTOP.
TIV[7:0] — Timer Interrupt Vector
This bit field contains the vector number that is generated during an IACK cycle in response to a timer
interrupt.
Table 14 Software Watchdog and Real-Time Clock Control Settings
Clock Control Setting
SWC[2:0]
RTC[2:0]
00
0
fsys/2
00
1
fref/2
01
0
fpre/1024
01
1
fpre/256
10
0
fpre/64
10
1
fpre/16
1
0
RTC Extension
RTC Off
1
SWDOG Off
RTC Off
f
pre
f
sys
2 if PCLK = 0
=
f
pre
f
ref
2 if PCLK = 1
=
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