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参数资料
| 型号： | SPMC16V1CPU20 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 121/128页 |
| 文件大小： | 571K |
| 代理商： | SPMC16V1CPU20 |
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MOTOROLA
MC68HC16V1
92
MC68HC16V1TS/D
There are variations within each phase for differing types of exceptions. However, all vectors but the
reset vectors contain 16-bit addresses, and the PK field is cleared. Exception handlers must be located
within bank 0 or vectors must point to a jump table.
4.7.4 Types of Exceptions
Exceptions can be either internally or externally generated. External exceptions, which are defined as
asynchronous, include interrupts, bus errors (BERR), breakpoints (BKPT), and resets (RESET). Inter-
nal exceptions, which are defined as synchronous, include the software interrupt (SWI) instruction, the
background (BGND) instruction, illegal instruction exceptions, and the divide-by-zero exception.
4.7.4.1 Asynchronous Exceptions
Asynchronous exceptions occur without reference to CPU16 or IMB clocks, but exception processing
is synchronized. For all asynchronous exceptions but RESET, exception processing begins at the first
instruction boundary following recognition of an exception.
Because of pipelining, the stacked return PK : PC value for all asynchronous exceptions, other than re-
set, is equal to the address of the next instruction in the current instruction stream plus $0006. The RTI
instruction, which must terminate all exception handler routines, subtracts $0006 from the stacked value
to resume execution of the interrupted instruction stream.
4.7.4.2 Synchronous Exceptions
Synchronous exception processing is part of an instruction definition. Exception processing for synchro-
nous exceptions is always completed, and the first instruction of the handler routine is always executed,
before interrupts are detected.
Because of pipelining, the value of PK : PC at the time a synchronous exception executes is equal to
the address of the instruction that causes the exception plus $0006. Because RTI always subtracts
$0006 upon return, the stacked PK : PC must be adjusted by the instruction that caused the exception
so that execution resumes with the following instruction. For this reason, $0002 is added to the PK : PC
value before it is stacked.
4.7.5 Multiple Exceptions
Each exception has a hardware priority based upon its relative importance to system operation. Asyn-
chronous exceptions have higher priorities than synchronous exceptions. Exception processing for mul-
tiple exceptions is completed by priority, from highest to lowest. Priority governs the order in which
exception processing occurs, not the order in which exception handlers are executed.
Unless a bus error, a breakpoint, or a reset occurs during exception processing, the first instruction of
all exception handler routines is guaranteed to execute before another exception is processed. Because
interrupt exceptions have higher priority than synchronous exceptions, the first instruction in an interrupt
handler is executed before other interrupts are sensed.
Bus error, breakpoint, and reset exceptions that occur during exception processing of a previous excep-
tion are processed before the first instruction of that exception’s handler routine. The converse is not
true. If an interrupt occurs during bus error exception processing, for example, the first instruction of the
exception handler is executed before interrupts are sensed. This permits the exception handler to mask
interrupts during execution.
4.7.6 RTI Instruction
The return-from-interrupt instruction (RTI) must be the last instruction in all exception handlers except
the RESET handler. RTI pulls the exception stack frame that was pushed onto the system stack during
exception processing, and restores processor state. Normal program flow resumes at the address of
the instruction that follows the last instruction executed before exception processing began.
RTI is not used in the RESET handler because RESET initializes the stack pointer and does not create
a stack frame.
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