参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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ADP1046
VOLTAGE SENSE AND CONTROL LOOP
Multiple voltage sense inputs on the ADP1046 are used for the
monitoring, control, and protection of the power supply output.
This information is available through the I 2 C interface. All voltage
sense points can be calibrated digitally to minimize errors due to
external components. This calibration can be performed in the
production environment, and the settings can be stored in the
For voltage monitoring, the VS1, VS2, and VS3 voltage value
registers (Register 0x15, Register 0x16, and Register 0x17,
respectively) are updated every 10 ms. The ADP1046 stores every
ADC sample for 10 ms and then outputs the average value at the
end of the 10 ms period. Therefore, if these registers are read at
least every 10 ms, a true average value is read.
The ADP1046 uses two separate sensing points: VS1 and VS3±,
depending on the condition of the OrFET. When the OrFET is
turned off, the control loop is regulated via VS1; when the OrFET
is turned on, the control loop is regulated via the differential
sensing on VS3±. This sensing mechanism effectively performs
a local and remote voltage sense.
The control loop of the ADP1046 features a patented multipath
architecture. The output voltage is converted simultaneously by
two ADCs: a high accuracy ADC and a high speed ADC. The
complete signal is reconstructed and processed in the digital
filter to provide a high performance, cost competitive solution.
Data Sheet
Σ-Δ ADCs also differ from Nyquist rate ADCs in that the quan-
tization noise is not uniform across the frequency spectrum. At
lower frequencies, the noise is lower, and at higher frequencies,
NYQUIST ADC
NOISE
Σ-Δ ADC
NOISE
FREQUENCY
Figure 17. Noise Performance for Nyquist Rate and Σ-Δ ADCs
The low frequency ADC runs at approximately 1.56 MHz. For a
specified bandwidth, the equivalent resolution can be calculated
as follows:
ln(1.56 MHz/ BW )/ln2 = N bits
For example, at a bandwidth of 95 Hz, the equivalent
resolution/noise is
ln(1.5 MHz/95)/ln2 = 14 bits
At a bandwidth of 1.5 kHz, the equivalent resolution/noise is
ln(1.56 MHz/1.5 kHz)/ln2 = 10 bits
The high frequency ADC has a clock of 25 MHz. It is comb
filtered and outputs at the switching frequency (f SW ) into the
digital filter. The equivalent resolution at some sample
12V
12V
12V
LOAD
Table 5. Equivalent Resolutions for High Frequency ADC
at Various Switching Frequencies
1V
1 1k?
1k?
1V
1 1k?
1k?
f SW (kHz)
48.8
High Frequency ADC Resolution
9 bits
97.7
8 bits
PGND
VS1
VS1 ADC
12 BITS
VS2 ADC
12 BITS
VS2
VS3 ADC
12 BITS
HF
VS3 ADC
VS3+
VS3–
1 1k?
1V
1k?
195.3 7 bits
390.6 6 bits
The HF ADC has a range of ±30 mV. Using a base switching
frequency (f SW ) of 100 kHz (8-bit HF ADC resolution), when f SW
increases to 200 kHz (7-bit HF ADC resolution), the quantization
noise is 0.9375 mV (1 LSB). Increasing f SW to 400 kHz increases the
DIGITAL
FILTER
quantization noise to 3.75 mV (1 LSB = 2 × 30 mV/2 6 = 0.9375 mV).
VS1 OPERATION (VS1)
ADCs
Figure 16. Voltage Sense Configuration
VS1 is used for the monitoring and protection of the power supply
voltage at the output of the LC stage, upstream of the OrFET. The
VS1 sense point on the power rail needs an external resistor
Two kinds of Σ-Δ ADCs are used in the feedback loop of the
and a high frequency (HF) ADC that runs at 25 MHz.
Σ-Δ ADCs have a resolution of one bit and operate differently
from traditional flash ADCs. The equivalent resolution obtain-
able depends on how long the output bit stream of the Σ-Δ is
sampled.
divider to bring the nominal input voltage to 1 V at the VS1 pin
(see Figure 16). The resistor divider is necessary because the VS1
ADC input range is 0 V to 1.6 V (12-bit reading). This divided-
down signal is internally fed into a low speed Σ-Δ ADC. The output
of the VS1 ADC goes to the digital filter and is also updated in
Register 0x15 every 10 ms. The VS1 signal is referenced to PGND.
When the OrFET is turned off, the power supply is regulated
from the VS1 sense point instead of the VS3± sense point.
Rev. B | Page 16 of 92
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