参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 70/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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ADP1046
Table 74. Register 0x4A—OUTC Rising Edge Setting (OUTC Pin)
Data Sheet
Bits
[7:4]
Bit Name
t 5
R/W
R/W
Description
These bits contain the four LSBs of the 12-bit t 5 time. This value is always used with the eight
bits of Register 0x49, which contains the eight MSBs of the t 5 time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t PERIOD ? 5 ns.
3
Modulate enable
R/W
1 = PWM modulation acts on the t 5 edge.
0 = no PWM modulation of the t 5 edge.
2
t 5 sign
R/W
1 = negative sign. Increase of PWM modulation moves t 5 right.
0 = positive sign. Increase of PWM modulation moves t 5 left.
1
0
Reserved
Volt-second balance
source selection
R/W
R/W
Reserved.
If this bit is set to 1, the OUTC rising edge is selected as the start of the integration period for
volt-second balance.
Table 75. Register 0x4B—OUTC Falling Edge Timing (OUTC Pin)
Bits
[7:0]
Bit Name
t 6
R/W
R/W
Description
This register contains the eight MSBs of the 12-bit t 6 time. This value is always used with the top
four bits of Register 0x4C, which contains the four LSBs of the t 6 time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t PERIOD ? 5 ns.
Table 76. Register 0x4C—OUTC Falling Edge Setting (OUTC Pin)
Bits
[7:4]
Bit Name
t 6
R/W
R/W
Description
These bits contain the four LSBs of the 12-bit t 6 time. This value is always used with the eight
bits of Register 0x4B, which contains the eight MSBs of the t 6 time. Each LSB corresponds to
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t PERIOD ? 5 ns.
3
Modulate enable
R/W
1 = PWM modulation acts on the t 6 edge.
0 = no PWM modulation of the t 6 edge.
2
t 6 sign
R/W
1 = negative sign. Increase of PWM modulation moves t 6 right.
0 = positive sign. Increase of PWM modulation moves t 6 left.
[1:0]
Reserved
R/W
Reserved.
Table 77. Register 0x4D—OUTD Rising Edge Timing (OUTD Pin)
Bits
[7:0]
Bit Name
t 7
R/W
R/W
Description
This register contains the eight MSBs of the 12-bit t 7 time. This value is always used with the
top four bits of Register 0x4E, which contains the four LSBs of the t 7 time. Each LSB corresponds
to 5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and
t_fall of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise
and t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value.
The absolute maximum pulse width is t PERIOD ? 5 ns.
Rev. B | Page 70 of 92
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