参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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ADP1046
LOGIC 1
LOGIC 0
Data Sheet
Round 1
In Round 1, every supply first places its MSB on the bus. If a
supply senses that its MSB is the same as the value on the bus, it
continues to Round 2. If a supply senses that its MSB is less than
the value on the bus, it means that this supply must be a slave.
When a supply becomes a slave, it stops communicating on the
IDLE
PREVIOUS
BIT
t 0
t 1
t BIT
NEXT
BIT
share bus because it knows that it is not the master. The supply
then increases its output voltage in an attempt to share more
current.
If two units have the same MSB, they both continue to Round 2
Figure 34. Share Bus High, Low, and Idle Bits
The length of a bit (t BIT ) is fixed at 10 μs. A Logic 1 is defined as
a high-to-low transition at the start of the bit and a low-to-high
transition at 75% of t BIT . A Logic 0 is defined as a high-to-low
transition at the start of the bit and a low-to-high transition at
25% of t BIT .
The bus is idle when it is high during the whole period of t BIT .
All other activity on the bus is illegal. Glitches up to t GLITCH
(200 ns) are ignored.
The digital word that represents the current information is eight
bits long. The ADP1046 takes the eight MSBs of the CS2 reading
and uses this reading as the digital word.
Digital Share Bus Scheme
Each power supply compares the digital word that it is outputting
with the digital words of all the other supplies on the bus.
PSU A
because either of them may be the master.
Round 2
In Round 2, all supplies that are still communicating on the bus
place their second MSB on the share bus. If a supply senses that
its MSB is less than the value on the bus, it means that this supply
must be a slave and it stops communicating on the share bus.
Round 3 to Round 8
The same algorithm is repeated for up to eight rounds to allow
supplies to compare their digital words and, in this way, to
determine whether each unit is the master or a slave.
Digital Share Bus Configuration
The digital share bus can be configured in various ways. The band-
width of the share bus loop is programmable in Register 0x29[2:0].
The extent to which a slave tries to match the current of the master
is programmable in Register 0x2A[3:0]. The primary side or the
secondary side current can be used as the current share signal
by programming Register 0x29[3].
V DD
8-BIT
WORD
MASTER
0x4A
SHAREi
SHARE
BUS
0xB5
I OUT = 35A
CS2+
1m ?
CS2–
+
35mV
–
CURRENT
SENSE
ADC
12 BITS
1195 DEC
0x4AB
DIGITAL
FILTER
÷16
8 BITS
74 DEC
0x4A
DIGITAL
WORD
SHAREo
0x4A 8-BIT
WORD
1 LSB = 29.3μV
35mV/29.3μV = 1195
Figure 35. How the Share Bus Generates the Digital Word to Place on the Digital Share Bus
Rev. B | Page 26 of 92
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