参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 38/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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ADP1046
Command Overview
Data Sheet
Data transfer using the I 2 C slave is established using commands.
S
W
A
COMMAND
CODE
A
Sr
R
A
All commands start with a slave address with the R/W bit cleared
(set to 0), followed by the command code (register address). All
commands supported by the ADP1046 follow one of the protocol
7-BIT SLAVE
COMMAND CODE
P
A
W
A
S
ADDRESS
BYTE
COUNT = N
= MASTER-TO-SLAVE
A
DATA
BYTE 1
A
...
DATA
BYTE N
NA
P
= SLAVE-TO-MASTER
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
Figure 46. Send Byte Protocol
Figure 52. Block Read Protocol
Clock Generation and Stretching
S
7-BIT SLAVE
ADDRESS
W
A
COMMAND
CODE
A
DATA
BYTE
A
P
The ADP1046 is always a slave in the overall system; therefore,
the device never needs to generate the clock, which is done by
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
Figure 47. Write Byte Protocol
the master device in the system. However, the I 2 C slave device is
capable of clock stretching to put the master in a wait state. By
stretching the SCL signal during the low period, the slave device
S
W
A
COMMAND
CODE
A
DATA
BYTE
LOW
A
DATA
BYTE
HIGH
A
P
communicates to the master device that it is not ready and that
the master device must wait.
Conditions where the I 2 C slave device stretches the SCL line low
= MASTER-TO-SLAVE
include the following:
= SLAVE-TO-MASTER
Figure 48. Write Word Protocol
?
?
The master device is transmitting at a higher baud rate
than the slave device.
The receive FIFO buffer of the slave device is full and must
S
W
A
COMMAND
CODE
A
Sr
R
A
be read before continuing. This prevents a data overflow
condition.
?
The slave device is not ready to send data that the master
has requested.
DATA BYTE
= MASTER-TO-SLAVE
NA
P
Note that the slave device can stretch the SCL line only during
the low period. Also, whereas the I 2 C specification allows indefinite
= SLAVE-TO-MASTER
Figure 49. Read Byte Protocol
stretching of the SCL line, the ADP1046 limits the maximum
time that the SCL line can be stretched, or held low. For more
information about the maximum time, see the Timeout
S
W
A
COMMAND
CODE
A
Sr
R
A
Condition section.
Start and Stop Conditions
Start and stop conditions involve serial data transitions while the
serial clock is at a logic high level. The I 2 C slave device monitors
DATA BYTE LOW
A
DATA BYTE HIGH
NA
P
the SDA and SCL lines to detect the start and stop conditions
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
Figure 50. Read Word Protocol
and transition its internal state machine accordingly. Typical
SCL
S
7-BIT SLAVE
ADDRESS
W
A
COMMAND
CODE
A
BYTE
COUNT = N
A
SDA
START
STOP
DATA BYTE 1
A
...
DATA BYTE N
A
P
Figure 53. Start and Stop Transitions
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
Figure 51. Block Write Protocol
Rev. B | Page 38 of 92
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