参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 30/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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ADP1046
5k?
CS2–
5k?
CS2+
Data Sheet
1V
ADC
12
ASYNCHRONOUS
2.62ms AVERAGING
PROGRAMMABLE DEBOUNCE
AND ACTION
(REG 0x0E AND REG 0x09)
200μA
200μA
CS2 ACCURATE
OCP SETTING
REG 0x26
Figure 39. CS2 OCP Detailed Internal Schematic
CS2 OCP
CS2 has one OCP protection circuit: CS2 accurate OCP (see
0x18) is compared to a programmable OCP threshold. The CS2
OCP threshold can be programmed using Register 0x26[7:0]. If
the CS2 reading exceeds the CS2 OCP threshold, the CS2 accurate
OCP flag is set. The CS2 ADC is asynchronously sampled, and
the readings are averaged every 2.62 ms to make a fault decision.
The flag response is programmed in Register 0x09.
CONSTANT CURRENT MODE
The ADP1046 can be configured to operate in constant current
mode. The threshold to enter constant current mode operation is
Below this current, the part operates in constant voltage mode,
using the output voltage as the feedback signal for closed-loop
operation.
V OUT
V OUT NOMINAL
0.97 × OCP I OUT
OCP
Figure 40. Constant Current Mode (V OUT vs. I OUT )
When the ADP1046 reaches the constant current mode threshold,
The constant current control loop is relatively low bandwidth
because the current is averaged over a 328 μs period. The output
voltage changes at a maximum rate of 1.18 V/sec at the VS3± pins;
therefore, the instantaneous value of the current can exceed the
constant current limit for a very short period of time, depend-
ing upon the transient.
As the output voltage falls, the UVP flag (Register 0x0B[3:0])
can be used to program a shutdown action.
OVERVOLTAGE PROTECTION (OVP)
The ADP1046 has three separate OVP circuits. If the output
voltage at the VS1 pin, VS2 pin, or VS3± pins exceeds the
programmable threshold for that pin, the appropriate OVP flag
is set. The flag response is programmed in Register 0x09[3:0]
for the VS2 and VS3 OVP flags or in Register 0x0A[7:4] for the
VS1 OVP flag.
VS1 has two OVP circuits: a fast comparator (fast OVP) and an
ADC based comparator (accurate OVP). VS2 and VS3 share an
accurate OVP circuit.
The OVP circuits can be programmed for different OVP
thresholds. See Register 0x32 and Register 0x33 for more
information.
The sampling time for the ADC based comparators is 80 μs.
Additional debounce in steps of 80 μs can be added using
Bits[1:0] of Register 0x32 and Register 0x33.
The fast OVP comparator also has a programmable threshold and
debounce time. These values are programmed in Register 0x37.
a flag is set in Register 0x02[4] and in Register 0x06[4] (real-time
and latched flag registers, respectively). When this flag is set,
the CS2 current reading is used to control the output voltage
regulation point. The output voltage is ramped down linearly as
the load increases to ensure that the current remains constant.
Rev. B | Page 30 of 92
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