参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 61/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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Data Sheet
Table 50. Register 0x32—VS1 Overvoltage Limit (OVP)
ADP1046
Bits
[7:3]
Bit Name
VS1 OVP setting
R/W
R/W
Description
Local overvoltage limit. This limit is programmable from 111.25% to 150% of the nominal VS1
voltage; 0x00 corresponds to 111.2%. Each LSB results in an increase of 1.25%. The VS1 OVP
threshold is calculated as follows:
VS1_OVP_Threshold = [(89 + VS1_OVP_Setting )/128] × 1.6 V
For example, if the VS1 OVP setting is 10, then
VS1_OVP_Threshold = [(89 + 10)/128] × 1.6 V = 1.2375 V
Setting these bits to 0 gives an OVP limit of 111.25% of the nominal VS1 voltage.
Setting these bits to 7 gives an OVP limit of 120% of the nominal VS1 voltage.
Setting these bits to 15 gives an OVP limit of 130% of the nominal VS1 voltage.
Setting these bits to 31 gives an OVP limit of 150% of the nominal VS1 voltage.
2
[1:0]
Reserved
OVP sampling
R/W
R/W
Reserved.
The OVP flag is set if the average voltage during the OVP sampling period is greater than the OVP
threshold. This OVP flag sampling period is 80 μs. The number of samples can be increased using
these bits. If the number of samples is increased, the average voltage must be greater than the
OVP threshold for each of those cycles. For example, if this value is set to two cycles, the average
voltage must be greater than the OVP threshold for both cycles.
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Additional Sampling (μs)
0 (one sample sets the OVP flag)
80 (two samples set the OVP flag)
160 (three samples set the OVP flag)
240 (four samples set the OVP flag)
Table 51. Register 0x33—VS2 and VS3 Overvoltage Limit (OVP)
Bits
[7:3]
Bit Name
VS2 and VS3
OVP setting
R/W
R/W
Description
Local overvoltage limit. This limit is programmable from 111.25% to 150% of the nominal VSx
voltage; 0x00 corresponds to 111.2%. Each LSB results in an increase of 1.25%. The VSx OVP
threshold is calculated as follows:
VSx_OVP_Threshold = [(89 + VSx_OVP_Setting )/128] × 1.6 V
For example, if the VS2 OVP setting is 10, then
VS2_OVP_Threshold = [(89 + 10)/128] × 1.6 V = 1.2375 V
Setting these bits to 0 gives an OVP limit of 111.25% of the nominal VSx voltage.
Setting these bits to 7 gives an OVP limit of 120% of the nominal VSx voltage.
Setting these bits to 15 gives an OVP limit of 130% of the nominal VSx voltage.
Setting these bits to 31 gives an OVP limit of 150% of the nominal VSx voltage.
2
Regulating point
R/W
When this bit is set, the ADP1046 regulates from the VS3 node at all times. When this bit is not set,
the ADP1046 uses the VS1 voltage as the regulating point during soft start and when the OrFET is
disabled.
[1:0]
OVP sampling
R/W
The OVP flag is set if the average voltage during the OVP sampling period is greater than the OVP
threshold. This OVP flag sampling period is 80 μs. The number of samples can be increased using
these bits. If the number of samples is increased, the average voltage must be greater than the
OVP threshold for each of those cycles. For example, if this value is set to two cycles, the average
voltage must be greater than the OVP threshold for both cycles.
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Additional Sampling (μs)
0 (one sample sets the OVP flag)
80 (two samples set the OVP flag)
160 (three samples set the OVP flag)
240 (four samples set the OVP flag)
Rev. B | Page 61 of 92
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