参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 55/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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Data Sheet
Table 32. Register 0x20—RTD Offset Trim (LSBs)
ADP1046
Bits
[7:0]
Bit Name
RTD offset trim (LSBs)
R/W
R/W
Description
These eight bits, together with Register 0x1C[0] (the MSB), set the amount of offset trim that
is applied to the RTD ADC reading.
CURRENT SENSE AND CURRENT LIMIT REGISTERS
Table 33. Register 0x21—CS1 Gain Trim
Bits
7
Bit Name
Gain polarity
R/W
R/W
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
[6:0]
CS1 gain trim
R/W
This value calibrates the primary side current sense gain. See the CS1 Trim section for more
information.
Table 34. Register 0x22—CS1 Accurate OCP Limit
Bits
[7:5]
Bit Name
CS1 fast OCP blanking
R/W
R/W
Description
These bits determine the blanking time for CS1 before fast OCP is enabled. This time is
measured from the start of a switching cycle. If using OUTAUX, the time is synchronized
with the rising edge of OUTAUX.
Bit 7
0
0
0
0
1
1
1
1
Bit 6
0
0
1
1
0
0
1
1
Bit 5
0
1
0
1
0
1
0
1
Delay (ns)
0
40
80
120
200
400
600
800
[4:0]
CS1 accurate OCP
R/W
These bits set the CS1 accurate OCP threshold. The digital word that is output from the CS1 ADC
is compared with this threshold. If the CS1 ADC reading (Register 0x13) is greater than the OCP
threshold set by these bits, the CS1 accurate OCP flag is set. This value should be programmed
only after the CS1 trim has been performed. The range of these bits is from 0 to 31, that is,
0 V to 1.4 V in 43.75 mV steps. The following equation gives the CS1 accurate OCP threshold:
CS1_OCP_Threshold = ( CS1_OCP_Limit × 1.4 V/32) + 16 × 1.4/2 12
Table 35. Register 0x23—CS2 Gain Trim
Bits
[7:6]
5
Bit Name
Reserved
Gain polarity
R/W
R/W
R/W
Description
Reserved.
1 = negative gain is introduced.
0 = positive gain is introduced.
[4:0]
CS2 gain trim
R/W
This register calibrates the secondary side (CS2) current sense gain. It calibrates for errors in
the sense resistor. See the CS2 Trim section for more information.
Table 36. Register 0x24—CS2 Analog Offset Trim
Bits
7
6
Bit Name
Reserved
Offset polarity
R/W
R/W
R/W
Description
Reserved.
1 = negative offset is introduced.
0 = positive offset is introduced.
[5:0]
CS2 offset trim
R/W
This register calibrates the secondary side (CS2) current sense common-mode error. It
calibrates for errors in the resistor divider network. See the CS2 Trim section for more
information.
Rev. B | Page 55 of 92
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