参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 62/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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ADP1046
Table 52. Register 0x34—VS1 Undervoltage Limit (UVP)
Data Sheet
Bits
7
Bit Name
End of cycle
shutdown
R/W
R/W
Description
This bit is valid only when the OUTAUX pin is used for regulation. When any flag shuts down the
power supply, the OUTAUX PWM is immediately shut down. This bit specifies when the other PWM
outputs are shut down.
1 = all other PWM outputs are shut down at the end of the switching cycle.
0 = all other PWM outputs are immediately shut down.
[6:0]
VS1 UVP setting
R/W
These bits set the UVP limit to one of 128 settings. The UVP limit can be programmed from 0% to
158.75% of the nominal VS1 voltage. Each LSB increases the voltage by 158.75%/128 = 1.25%. In
reality, there are 81 usable settings, which program the UVP threshold from 0% to 100% of the
nominal VS1 voltage. The VS1 UVP threshold is calculated as follows:
VS1_UVP_Threshold = [( VS1_UVP_Setting + 1)/128] × 1.6 V ? 12.5 mV
For example, if the VS1 UVP setting is 60, then
VS1_UVP_Threshold = [(60 + 1)/128] × 1.6 V ? 12.5 mV = 750 mV
Setting these bits to 0 gives a UVP limit of 0% of the nominal VS1 voltage.
Setting these bits to 72 (0x48) gives a UVP limit of 90% of the nominal VS1 voltage.
Setting these bits to 76 (0x4C) gives a UVP limit of 95% of the nominal VS1 voltage.
Setting these bits to 80 (0x50) gives a UVP limit of 100% of the nominal VS1 voltage.
Setting these bits to 127 (0x7F) gives a UVP limit of 158.75% of the nominal VS1 voltage.
Table 53. Register 0x35—Line Impedance Limit
Bits
[7:0]
Bit Name
Line impedance
limit
R/W
R/W
Description
This value sets the threshold at which the line impedance flag is enabled. This 8-bit value is
compared with the line impedance value (Register 0x1F). If the line impedance value exceeds this
value, the line impedance flag is set (Register 0x02, Bit 2).
Table 54. Register 0x36—Load Line Impedance
Bits
7
[6:4]
Bit Name
Load line enable
Slew rate
R/W
R/W
R/W
Description
Set this bit to enable the load line.
These bits set the load line slew rate limit, which determines the maximum slew rate for changing
the reference when adjusting the output load line value.
Bit 6
0
0
0
0
1
1
1
1
Bit 5
0
0
1
1
0
0
1
1
Bit 4
0
1
0
1
0
1
0
1
Maximum Slew Rate Duration
200 mV/ms
100 mV/ms
50 mV/ms
25 mV/ms
12.5 mV/ms
6.25 mV/ms
3.125 mV/ms
1.5625 mV/ms (4 LSB/ms)
3
[2:0]
Reserved
Load line setting
R/W
R/W
Reserved.
These bits specify how much the output voltage decreases from nominal at full load. The amount
of output resistance introduced can be calculated as follows (these bits specify the value of N ):
R OUT = 0.1 × V OUT_NOM × CS2 R SENSE /( CS2 Range × 2 N ).
For more i nformation , see the Digital Load Line and Slew Rate section.
Bit 2
0
0
0
0
1
1
1
1
Bit 1
0
0
1
1
0
0
1
1
Bit 0
0
1
0
1
0
1
0
1
Impedance Setting
Setting 0
Setting 1
Setting 2
Setting 3
Setting 4
Setting 5
Setting 6
Setting 7
Rev. B | Page 62 of 92
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