参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 85/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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Data Sheet
RESONANT MODE OPERATION
The ADP1046 supports control of a resonant converter.
Resonant converters are an alternative to traditional fixed
frequency converters. They offer high switching frequency,
small size, and high efficiency. Figure 58 illustrates a widely
used series resonant converter.
ADP1046
SYNCHRONOUS RECTIFICATION IN RESONANT
MODE
Control of the synchronous rectifiers in a resonant controller is
a complicated issue. The ADP1046 ACSNS comparator can be
used to control the SR signals. In resonant mode operation, the
Q A
Q C
SR2
SR1 output is driven by the rising edge of the ACSNS comparator,
and the SR2 output is driven by the falling edge of the comparator,
C R
L R
I O
Q D
Q B
I R
SR1
C O
R L
V DS (SR2)
Figure 58. Series Resonant Converter
RESONANT MODE ENABLE
ACSNS
To enable the ADP1046 to control a resonant switching con-
SYNC RECT 1 (SR1)
Δ t 9
Δ t 10
verter, Register 0x40 must be set to a value of 0x3F. In resonant
mode, the PWM outputs have a fixed duty cycle with variable
frequency.
SYNC RECT 2 (SR2)
Δ t 11
Δ t 12
PWM TIMING IN RESONANT MODE
With variable frequency control, OUTA and OUTB can only be
high during the first half of the switching cycle (t A to t B ), whereas
OUTC and OUTD can only be high during the second half of
the switching cycle (t B to t C ), as shown in Figure 59. The
frequency resolution of the control law is in steps of 10 ns.
t D t E t F
Figure 60. SR1 and SR2 PWM Timing Diagram in Resonant Mode
Following is an example of how the ADP1046 can be used in a
series resonant topology and also achieve control of the synchro-
nous rectifiers. The V DS voltage of SR2 (see Figure 60) can be
used to control the SR signals. The ACSNS pin is connected to
PWM1 (OUTA)
Δ t 1
Δ t 2
the divided-down SR2 V DS voltage. This provides the timing
SR2
R 1
PWM2 (OUTB)
Δ t 3
Δ t 4
C R
L R
I O
R 2
ACSNS
I R
SR1
C O
R L
PWM3 (OUTC)
Δ t 5
Δ t 6
Figure 61. Resonant Synchronous Rectifier Control Circuit
After the timing information is obtained, SR1 is driven by the
PWM4 (OUTD)
Δ t 7
Δ t 8
rising edge of the ACSNS comparator, and SR2 is driven by the
falling edge of the comparator, as shown in Figure 60. In this
way, it is possible to achieve synchronous rectification. Turn-on
t PERIOD
t PERIOD
and turn-off delays can be programmed for the SR1 and SR2
t A
t B
t C
signals individually.
Figure 59. OUTA, OUTB, OUTC, and OUTD PWM Timing Diagram
in Resonant Mode
This example is not the only way to control the SR signals. If the
user has another method to control the SR signals, this method
can be used to connect to the ACSNS input instead of the V DS
voltage of SR2.
When the ADP1046 is used to control a resonant converter, it is
recommended that SR soft start be disabled during soft start of
the device (set Register 0x0F[7] = 1).
Rev. B | Page 85 of 92
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