参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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Data Sheet
Temperature Linearization Scheme
The ADP1046 implements a linearization scheme based on a
preselected combination of thermistor (100 k?, 1%), external
resistor (16.5 k?, 1%), and the 46 μA current source for best
performance when linearizing measured temperatures in the
industrial range.
The required NTC thermistor should have a resistance of
100 k?, 1%, such as the NCP15WF104F03RC (beta = 4250,
1%). It is recommended that 1% tolerance be used for both the
resistor and beta values.
Reading the Linearized Temperature
Reading Register 0x1B (updated every 10 ms) returns the current
temperature according to an internal linearization scheme. See
temperature reading result is represented in 8-bit decimal format
in °C; therefore, the temperature range for this reading is from
0 ° C to 255 ° C.
OVERTEMPERATURE PROTECTION (OTP)
If the temperature sensed at the RTD pin exceeds the threshold
programmed in Register 0x2F, the OTP flag is set. The response
to the OTP flag is programmable using Register 0x0B[7:4].
An RTD trim is required to make accurate temperature readings
at the lower end of the RTD ADC range to account for tolerances
in the NTC thermistor and the external resistor. This trim results
in a more accurate measurement for determining the OTP
threshold (see the RTD/OTP Trim section).
ADP1046
OVERCURRENT PROTECTION (OCP)
The ADP1046 has several OCP functions. CS1 and CS2± have
separate OCP circuits to provide both primary and secondary
side protection.
CS1 OCP
CS1 has two protection circuits: CS1 fast OCP and CS1 accurate
CS1 Fast OCP
CS1 fast OCP is an analog comparator. When the voltage at the
CS1 pin exceeds the (fixed) 1.2 V threshold, the CS1 fast OCP
flag is set. A programmable blanking time can be set to ignore
the leading edge current spike at the beginning of the current
signal (leading edge blanking).
A debounce time can be programmed to improve the noise immu-
nity of the OCP circuit. When the CS1 fast OCP comparator is
set, the OUTA, OUTB, OUTC, and OUTD PWM outputs are
immediately disabled for the remainder of the switching cycle.
These outputs are reenabled at the start of the next switching
cycle. This function cannot be bypassed.
CS1 Accurate OCP
CS1 accurate OCP is used for more precise control of overcurrent
protection. With CS1 accurate OCP, the reading at the output of
the CS1 ADC (Register 0x13) is compared to a programmable
OCP limit. The CS1 accurate OCP value can be programmed
from 0 to 31 decimal using Register 0x22[4:0]. If the CS1 reading
exceeds the CS1 accurate OCP limit, the CS1 accurate OCP flag
is set. The CS1 ADC is asynchronously sampled, and the readings
are averaged every 2.62 ms to make a fault decision. The flag
response is programmed in Register 0x08.
V IN
OUTA
OUTB
OUTC
OUTD
CS1
CS1
ADC
12
ASYNCHRONOUS
2.62ms AVERAGING
CS1 ACCURATE
OCP SETTING
CS1 ACCURATE
OCP FLAG
CS1 FAST
OCP
FLAG
FLAGS
SHUTDOWN
REG 0x22[4:0]
OUTA
OUTB
1.2V
CS1
FAST OCP
BYPASS
CS1
FAST OCP
BLANKING
CS1
FAST OCP
DEBOUNCE
CYCLE
TIMEOUT
CYCLE-BY-CYCLE
SHUTDOWN
PWM
OUTC
OUTD
FAST OCP
COMPARATOR
REG 0x27[4]
REG 0x22[7:5] REG 0x27[7:6] REG 0x27[1:0]
SR1
SR2
OUTAUX
FLAGIN
Figure 38. CS1 OCP Detailed Internal Schematic
Rev. B | Page 29 of 92
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