参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 49/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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Data Sheet
ADP1046
DETAILED REGISTER DESCRIPTIONS
FAULT REGISTERS
Register 0x04 to Register 0x07 are latched fault registers. In these registers, flags are not reset when the fault disappears. Flags are cleared
only by a register read (provided that the fault no longer persists). Note that latched bits are clocked on a low-to-high transition only. Also
note that these register bits are cleared when read via the I 2 C interface unless the fault is still present. It is recommended that the latched
fault register be read again after the faults disappear to ensure that the register is reset.
Table 8. Register 0x00—Fault Register 1 and Register 0x04—Latched Fault Register 1 (1 = Fault, 0 = Normal Operation)
Bits
7
Bit Name
Power supply
R/W
R
Description
1 = power supply is off. All PWM outputs are disabled. This bit
Register
Action
None
stays high until the power supply is restarted.
6
OrFET
R
1 = OrFET control signal at the GATE pin (Pin 16) is off.
0x30
5
PGOOD1 fault
R
1 = Power-Good 1 fault. At least one of the following flags has been
0x2D
None
set: soft start flag, CS1 fast OCP, CS1 accurate OCP, CS2 accurate OCP,
UVP, local OVP, load OVP, or OrFET (GATE pin). These flags can be
masked using Register 0x7B.
4
PGOOD2 fault
R
1 = Power-Good 2 fault. At least one of the following flags has been
set: soft start flag, CS1 fast OCP, CS1 accurate OCP, CS2 accurate OCP,
0x2D
None
UVP, local OVP, load OVP, or OrFET (GATE pin). These flags can be
masked using Register 0x7C.
The following flags can also set PGOOD2, either unconditionally
or based on the flag response, as defined in Register 0x2D[3] (see
(FLAGIN pin), and OTP.
3
SR off
R
SR1 and SR2 synchronous rectifiers are disabled. This flag is set
None
when one of the following cases is true:
SR1 and SR2 are disabled by the user.
The load current has fallen below the threshold in Register 0x3B.
A flag has been set that is configured to disable the synchronous
rectifiers.
0x5D
0x3B
0x08 to
0x0D
2
CS1 fast OCP
R
CS1 current is above its fast overcurrent protection limit. There is a
Programmable
1.2 V threshold on the CS1 pin. Fast OCP is a comparator.
1
0
CS1 accurate OCP
CS2 accurate OCP
R
R
CS1 current is above its accurate overcurrent protection limit.
CS2 current is above its accurate overcurrent protection limit.
0x22
0x26
Programmable
Programmable
Table 9. Register 0x01—Fault Register 2 and Register 0x05—Latched Fault Register 2 (1 = Fault, 0 = Normal Operation)
Bits
7
Bit Name
Voltage
continuity
R/W
R
Description
Voltage differential between VS1 and VS2 pins or between VS2
and VS3± pins is outside limits. Either (VS1 ? VS2) > 50 mV or
Register
Action
Programmable
(VS2 ? VS3) > 50 mV at the pins.
6
5
UVP
CS2 reverse
R
R
VS1 is below its undervoltage limit.
Reverse voltage across the CS2± pins is above limit. This is the
0x34
0x30
Programmable
Programmable
current
OrFET reverse voltage.
4
3
VDD UV
VCORE OV
R
R
VDD is below limit.
2.5 V VCORE is above limit.
Immediate shutdown
Immediate shutdown
2
VDD OV
R
VDD is above limit. The I 2 C interface stays functional, but a PSON
0x0E
Programmable
toggle is required to restart the power supply.
1
0
Load OVP
Local OVP
R
R
VS2 or VS3± is above its overvoltage limit.
VS1 is above its overvoltage limit.
0x33
0x32
Programmable
Programmable
Rev. B | Page 49 of 92
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