参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 88/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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ADP1046
Table 158. Register 0x45—OUTB Rising Edge Dead Time in Resonant Mode
Data Sheet
Bits
[7:0]
Bit Name
Δt 3 (rising edge dead
time of OUTB)
R/W
R/W
Description
This register sets Δt 3 , which is the delay time of the rising edge of OUTB from the start of the
switching cycle, t A . Each LSB corresponds to 5 ns of resolution.
Bit 7
0
0
…
1
Bit 6
0
0
…
1
Bit 5
0
0
…
1
Bit 4
0
0
…
1
Bit 3
0
0
…
1
Bit 2
0
0
…
1
Bit 1
0
0
…
1
Bit 0
0
1
…
1
Δt 3 (ns)
0
5
…
1275
Table 159. Register 0x46—Highest Switching Frequency Limit Setting (Minimum Switching Cycle in Resonant Mode)
Bits
[7:0]
Bit Name
Highest frequency
R/W
R/W
Description
This register contains the eight MSBs of the 12-bit value of the highest switching frequency (mini-
mum switching cycle) limit. This value is always used with the top four bits of Register 0x48,
which contain the four LSBs of the highest switching frequency limit. Each LSB of the 12-bit
value corresponds to 5 ns of resolution for the switching cycle. For example, if Register 0x46
is set to 0x10 (16 decimal) and Bits[7:4] of Register 0x48 are set to 0x9 (9 decimal), the minimum
switching cycle is (16 × 16 + 9) × 5 ns = 1.325 μs, and the highest switching frequency limit is
1/1.325 μs = 755 kHz. It is recommended that the maximum frequency be limited to 1 MHz.
Table 160. Register 0x47—OUTB Falling Edge Dead Time in Resonant Mode
Bits
[7:0]
Bit Name
Δt 4 (falling edge dead
time of OUTB)
R/W
R/W
Description
This register sets Δt 4 , which is the difference between the falling edge of OUTB and the mid-
point of the switching cycle, t B . Each LSB corresponds to 5 ns of resolution. When the register
value is from 0x00 to 0x7F, the falling edge of OUTB is trailing t B . When the value is from 0x80
to 0xFF, t he falling edge of OUTB is leading t B .
Bit 7
0
0
…
0
1
…
1
Bit 6
0
0
…
1
0
…
1
Bit 5
0
0
…
1
0
…
1
Bit 4
0
0
…
1
0
…
1
Bit 3
0
0
…
1
0
…
1
Bit 2
0
0
…
1
0
…
1
Bit 1
0
0
…
1
0
…
1
Bit 0
0
1
…
1
0
…
1
Δt 4
0 ns
5 ns trailing
…
635 ns trailing
640 ns leading
…
5 ns leading
Table 161. Register 0x48—Highest Switching Frequency Limit Setting (Minimum Switching Cycle in Resonant Mode)
Bits
[7:4]
Bit Name
Highest frequency
R/W
R/W
Description
This register contains the four LSBs of the 12-bit value of the highest switching frequency (mini-
mum switching cycle) limit. This value is always used with the eight bits of Register 0x46, which
contain the eight MSBs of the highest switching frequency limit. Each LSB of the 12-bit value
corresponds to 5 ns of resolution for the switching cycle. For example, if Register 0x46 is set to
0x10 (16 decimal) and Bits[7:4] of Register 0x48 are set to 0x9 (9 decimal), the minimum
switching cycle is (16 × 16 + 9) × 5 ns = 1.325 μs, and the highest switching frequency limit is
1/1.325 μs = 755 kHz.
[3:0]
Reserved
R/W
Reserved.
Rev. B | Page 88 of 92
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