参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 32/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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ADP1046
VOLT-SECOND BALANCE
The ADP1046 has a dedicated circuit to maintain volt-second
balance in the main transformer when operating in full-bridge
topology. This circuit eliminates the need for a dc blocking capac-
itor. In interleaved topologies, volt-second balance can also be
used for current balancing to ensure that each interleaved phase
contributes equal power.
The circuit monitors the current flowing in both legs of the full-
bridge topology and stores this information. It compensates the
selected PWM signals to ensure equal current flow in both legs
of the full-bridge topology. The input is through the CS1 pin.
Several switching cycles are required for the circuit to operate
effectively. The maximum amount of modulation applied to
each edge of the selected PWM outputs is programmable to
±80 ns or ±160 ns in Register 0x28[2].
The volt-second balance settings are programmed in Register 0x28
Data Sheet
For example, if V OUT_NOM = 12 V, CS2 R SENSE = 10 m?,
CS2 Range = 120 mV, and LOAD_SET[2:0] = 3,
R OUT = 0.1 × 12 V × 10 m?/(120 mV × 2 3 ) = 12.5 m?
This feature can be used for advanced current sharing techniques.
By default, the load line is disabled. The load line is introduced
digitally by modifying the value of the digital reference based
on the CS2 reading.
V OUT vs. the R SENSE voltage drop.
100
99
98
97
96
95
and in Register 0x76 through Register 0x78. It is recommended
that the Analog Devices software GUI be used to program these
settings.
The compensation of the PWM drive signals is performed on
94
93
92
91
SETTING
SETTING
SETTING
SETTING
SETTING
SETTING
SETTING
7
6
5
4
3
2
1
the edges of two selected outputs. The SR1 and SR2 edges can
also be independently set to modulate due to the volt-second
balance circuit to maintain the timing relation to the primary
side signals.
DIGITAL LOAD LINE AND SLEW RATE
The ADP1046 can optionally introduce a digital load line into
the power supply. This option is programmed in the load line
impedance register (Register 0x36). Two parameters can be
configured independently: slew rate and load line value.
The slew rate (Register 0x36[6:4]) determines how quickly the
output voltage is adjusted in response to a change in the digital
90
100
98
96
94
SETTING 0
0 10 20 30 40 50 60 70 80 90 100 110 120
R SENSE VOLTAGE DROP (mV)
Figure 42. Load Line Settings with 120 mV CS2 Range
reference. Eight different settings are available.
The load line value (Register 0x36[2:0]) controls the slope of
the load line. The amount of output resistance introduced can
be calculated as follows:
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SETTING
SETTING
SETTING
SETTING
SETTING
SETTING
SETTING
7
6
5
4
3
2
1
R OUT = 0.1 × V OUT_NOM × CS2 R SENSE /( CS2 Range × 2 LOAD_SET[2:0] )
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0
5
SETTING 0
10 15
20
25
30
35
40
45
50
55
60
where:
V OUT_NOM is the nominal output voltage when VS3 = 1 V.
CS2 R SENSE is the sense resistor value.
CS2 Range is 120 mV or 60 mV.
LOAD_SET[2:0] is the value of Bits[2:0] in Register 0x36
(0 to 7 decimal).
Rev. B | Page 32 of 92
R SENSE VOLTAGE DROP (mV)
Figure 43. Load Line Settings with 60 mV CS2 Range
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| ADP1046ADC1-EVALZ | 功能描述:电源管理IC开发工具 RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
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