参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 58/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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ADP1046
Table 44. Register 0x2C—PSON/Soft Start
Data Sheet
Bits
[7:6]
Bit Name
PS_ON setting
R/W
R/W
Description
These bits determine which signal is used by the ADP1046 as the PS_ON control.
Bit 7
Bit 6
PS_ON Setting
0
0
The ADP1046 is always on.
0
1
Hardware PSON pin is used to enable or disable the power supply.
1
0
Software PS_ON bit (Bit 5) is used to enable or disable the power supply.
1
1
Both the software PS_ON bit and the hardware PSON pin must be enabled
before the ADP1046 is enabled.
5
PS_ON
R/W
Software PS_ON bit.
0 = power supply off.
1 = power supply on.
[4:3]
2
1
0
PS_ON delay
Reserved
Disable light load
during soft start
Force soft start
filter
R/W
R/W
R/W
R/W
These bits set the time from when the PS_ON control signal is set to when the soft start begins.
Bit 4
Bit 3
Typical Delay (sec)
0
0
0
0
1
0.5
1
0
1
1
1
2
Set this bit to 0 for normal operation.
0 = allow switching to light load mode filter during soft start.
1 = never switch to light load mode filter during soft start.
0 = use normal mode filter or soft start filter, depending on the OrFET status. If regulating from
VS3 (OrFET on), the normal mode filter is used. If regulating from VS1 (OrFET off ), the soft start
filter is used.
1 = use soft start filter as the initial filter regardless of OrFET status.
Table 45. Register 0x2D—PGOOD Debounce and Pin Polarity Settings
Bits
[7:6]
Bit Name
PGOOD1 turn-on
debounce
R/W
R/W
Description
These bits set the debounce time before the PGOOD1 pin and flag are set. This debounce time
starts at the end of the soft start ramp and can vary by ±50 ms. The turn-off of PGOOD1 is always
immediate (no debounce).
Bit 7
0
0
1
1
Bit 6
0
1
0
1
Typical Debounce Time (ms)
350
150
550
0
[5:4]
PGOOD2 turn-on
debounce
R/W
These bits set the debounce time before the PGOOD2 pin and flag are set. This debounce time
starts at the end of the soft start ramp and can vary by ±50 ms. The turn-off of PGOOD2 is always
immediate (no debounce).
Bit 5
0
0
1
1
Bit 4
0
1
0
1
Typical Debounce Time (ms)
350
150
550
0
3
PGOOD2 flags
R/W
The following flags can also set the PGOOD2 pin: voltage continuity, OrFET disable, ACSNS, FLAGIN,
and OTP. This bit specifies whether these flags unconditionally set PGOOD2 or whether these flags
set PGOOD2 only if the flag action is not set to ignore (Bits[6:4] = 000) in the appropriate fault
0 = voltage continuity, OrFET disable, ACSNS, FLAGIN, and OTP flags always set the PGOOD2 pin.
1 = voltage continuity, OrFET disable, ACSNS, FLAGIN, and OTP flags set the PGOOD2 pin only if the
flag action is not set to ignore.
2
1
0
FLAGIN polarity
GATE polarity
PSON polarity
R/W
R/W
R/W
This bit sets the polarity of the FLAGIN input pin: 1 = inverted (low = 0 V = on).
This bit sets the polarity of the OrFET GATE control pin: 1 = inverted (low = 0 V = on).
This bit sets the polarity of the PSON input pin: 1 = inverted (low = 0 V = on).
Rev. B | Page 58 of 92
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