参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 57/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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Data Sheet
ADP1046
Bits
2
Bit Name
Volt-second balance
modulation
R/W
R/W
Description
This bit specifies the maximum amount of modulation from volt-second balance.
0 = ±80 ns maximum.
1 = ±160 ns maximum.
[1:0]
Volt-second balance
gain setting
R/W
These bits set the gain of the volt-second balance circuit. The gain can be changed by a factor of
64. When these bits are set to 00, it takes approximately 700 ms to achieve volt-second balance.
When these bits are set to 11, it takes approximately 10 ms to achieve volt-second balance.
Bit 1
0
0
1
1
Table 41. Register 0x29—Share Bus Bandwidth
Bit 0
0
1
0
1
Volt-Second Balance Gain
1
4
16
64
Bits
[7:5]
4
Bit Name
Reserved
Bit stream
R/W
R/W
R/W
Description
Reserved.
1 = the current sense ADC reading is output on the SHAREo pin. This bit stream can be used for
analog current sharing.
0 = the digital share bus signal is output on the SHAREo pin. This signal can be used for digital
current sharing.
3
Current share
R/W
1 = Reserved.
0 = CS2 reading used for current share.
[2:0]
Share bus bandwidth
R/W
These bits determine the amount of bandwidth dedicated to the share bus. The value 000 is
the lowest possible bandwidth, and the value 111 is the highest possible bandwidth.
The slave moves up 1 LSB for every share bus transaction (8 data bits plus start and stop bits).
The master moves down x LSBs per share bus transaction, where x is the share bus register
setting 0x2A[7:4].
0 = divide LSB by 16, that is, 1 LSB = 24 μV/16
1 = divide LSB by 8
2 = divide LSB by 4
3 = divide LSB by 2
4 = nominal
5 = multiply LSB by 2
6 = multiply LSB by 4
7 = multiply LSB by 8
8 = multiply LSB by 16
Table 42. Register 0x2A—Share Bus Setting
Bits
[7:4]
[3:0]
Bit Name
Number of bits
dropped by master
Bit difference between
master and slave
R/W
R/W
R/W
Description
These bits determine how much a master device reduces its output voltage to maintain
current sharing.
These bits determine how closely a slave tries to match the current of the master device. The
higher the setting, the larger the voltage difference that satisfies the current sharing criteria.
Table 43. Register 0x2B—Temperature Gain Trim
Bits
7
Bit Name
Gain polarity
R/W
R/W
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
[6:0]
Gain trim
R/W
This register calibrates the RTD ADC gain. It calibrates for errors in the ADC.
Rev. B | Page 57 of 92
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