参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 79/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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Data Sheet
Table 119. Register 0x77—Volt-Second Balance Settings (OUTC and OUTD Pins)
ADP1046
Bits
7
Bit Name
Modulate enable, t 5
R/W
R/W
Description
Setting this bit enables modulation from balance control on the OUTC rising edge, t 5 . It is not
recommended to allow volt-second balance on edges that are between 0 ns to 640 ns of the
switching period.
6
t 5 sign
R/W
0 = positive sign. Increase of balance control modulation moves t 5 right.
1 = negative sign. Increase of balance control modulation moves t 5 left.
5
Modulate enable, t 6
R/W
Setting this bit enables modulation from balance control on the OUTC falling edge, t 6 . It is not
recommended to allow volt-second balance on edges that are between 0 ns to 640 ns of the
switching period.
4
t 6 sign
R/W
0 = positive sign. Increase of balance control modulation moves t 6 right.
1 = negative sign. Increase of balance control modulation moves t 6 left.
3
Modulate enable, t 7
R/W
Setting this bit enables modulation from balance control on the OUTD rising edge, t 7 . It is not
recommended to allow volt-second balance on edges that are between 0 ns to 640 ns of the
switching period.
2
t 7 sign
R/W
0 = positive sign. Increase of balance control modulation moves t 7 right.
1 = negative sign. Increase of balance control modulation moves t 7 left.
1
Modulate enable, t 8
R/W
Setting this bit enables modulation from balance control on the OUTD falling edge, t 8 . It is not
recommended to allow volt-second balance on edges that are between 0 ns to 640 ns of the
switching period.
0
t 8 sign
R/W
0 = positive sign. Increase of balance control modulation moves t 8 right.
1 = negative sign. Increase of balance control modulation moves t 8 left.
Table 120. Register 0x78—Volt-Second Balance Settings (SR1 and SR2 Pins)
Bits
7
Bit Name
Modulate enable, t 9
R/W
R/W
Description
Setting this bit enables modulation from balance control on the SR1 rising edge, t 9 . It is not
recommended to allow volt-second balance on edges that are between 0 ns to 640 ns of the
switching period.
6
t 9 sign
R/W
0 = positive sign. Increase of balance control modulation moves t 9 right.
1 = negative sign. Increase of balance control modulation moves t 9 left.
5
Modulate enable, t 10
R/W
Setting this bit enables modulation from balance control on the SR1 falling edge, t 10 . It is not
recommended to allow volt-second balance on edges that are between 0 ns to 640 ns of the
switching period.
4
t 10 sign
R/W
0 = positive sign. Increase of balance control modulation moves t 10 right.
1 = negative sign. Increase of balance control modulation moves t 10 left.
3
Modulate enable, t 11
R/W
Setting this bit enables modulation from balance control on the SR2 rising edge, t 11 . It is not
recommended to allow volt-sec balance on edges that are between 0 ns to 640 ns of the
switching period.
2
t 11 sign
R/W
0 = positive sign. Increase of balance control modulation moves t 11 right.
1 = negative sign. Increase of balance control modulation moves t 11 left.
1
Modulate enable, t 12
R/W
Setting this bit enables modulation from balance control on the SR2 falling edge, t 12 . It is not
recommended to allow volt-second balance on edges that are between 0 ns to 640 ns of the
switching period.
0
t 12 sign
R/W
0 = positive sign. Increase of balance control modulation moves t 12 right.
1 = negative sign. Increase of balance control modulation moves t 12 left.
Table 121. Register 0x79—SR Delay Compensation
Bits
[7:6]
[5:0]
Bit Name
Reserved
SR driver delay
R/W
R/W
R/W
Description
Reserved.
These bits specify the 6-bit representation of the SR delay in steps of 5 ns.
000000 = 0 ns.
111111 = 63 ns × 5 ns = 315 ns.
Rev. B | Page 79 of 92
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