参数资料
| 型号： | ADP1046ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/92页 |
| 文件大小： | 0K |
| 描述： | IC DGTL CTRLR 32LFCSP |
| 标准包装： | 5,000 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.6 V |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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ADP1046
SOFT START
The turning on and off of the ADP1046 is controlled by the
hardware PSON pin and/or the software PSON register,
depending on the configured settings in Register 0x2C.
When the user turns on the power supply (enables PSON),
Data Sheet
Digital Compensation Filters During Soft Start
The ADP1046 has a dedicated soft start filter (SSF) that can be
used to fine-tune and optimize the dynamic response during
the output voltage ramp-up.
Before it ramps up the internal reference after the PSON signal
is enabled, the ADP1046 evaluates whether the OrFET should
1.
2.
3.
4.
5.
6.
The PSON signal is enabled at Time t 0 . If the part is
programmed to be always on (Register 0x2C[7:6] = 00),
PSON is enabled as soon as VCORE is above UVLO.
The ADP1046 waits for the programmed PS_ON delay
(set in Register 0x2C[4:3]).
The soft start begins to ramp up the internal digital refer-
ence. The total duration of the soft start ramp is program-
mable from 5 ms to 100 ms using Register 0x5F[7:5].
If the soft start from precharge function is enabled
(Register 0x5F[4] = 1), the soft start ramp starts from
the value of the output voltage sensed on VS1 or VS3±
(depending on the OrFET status), and the soft start ramp
time is reduced proportionally. If the soft start from pre-
charge function is disabled, the soft start ramp time is the
programmed value in Register 0x5F[7:5].
When the power supply voltage exceeds the VS1 under-
voltage protection (UVP) limit (set in Register 0x34[6:0]),
the UVP flag is reset.
The OrFET is turned on as soon as the OrFET enable thresh-
old is met. (The OrFET enable threshold is programmed in
be turned on or off by looking at the difference between VS1
and VS2. This step is done to determine whether the regulation
? If the regulation point is VS1, the soft start filter is used
by default during the ramp-up. At the end of the soft start
ramp, the part switches to the normal mode filter (NMF).
? If the regulation point is VS3±, the part starts the ramp
using the normal mode filter (NMF).
In both cases, after the voltage reaches 12.5% of the nominal
output voltage value, the load current is evaluated.
? If the load current is below the light load mode threshold,
the part switches to the light load mode filter (LLF).
? If the load current is above the light load mode threshold,
the normal mode filter is used until the end of the soft start
ramp, even if the system subsequently enters light load
mode based on a change to the load current.
Register 0x2C can be programmed to configure the use of the
different filters during soft start as follows:
7.
8.
Register 0x30[6:5].) The regulation point is switched from
VS1 to VS3±.
If no other fault conditions are present, the PGOODx
signals wait for the programmed debounce time (set in
Register 0x2D[7:4]) and are then enabled. The soft start
flag must be unmasked in Register 0x7B and Register 0x7C
(Bit 7 must be set to 0).
If no OrFET is used, the power supply must be configured
to regulate using VS3 at all times (Register 0x33[2] = 1).
VS2 can be used as a secondary OVP mechanism.
?
?
Force soft start filter (Bit 0). This option forces the part to
use the soft start filter even when the regulation point is
VS3. In some cases, this option allows better fine-tuning of
the ramp-up voltage. This option can also be selected when
an OrFET is not used.
Disable light load mode during soft start (Bit 1). This
option prevents the use of the light load mode filter during
soft start, even if the light load condition is met. The light
load mode filter is available for use after the end of the soft
start ramp.
Fault Condition During Soft Start
If a fault condition occurs during soft start, the controller responds
as programmed unless the flag is blanked. Flag blanking during
soft start is programmed in Register 0x0F. The ACSNS flag is
always blanked during soft start. The OTP, FLAGIN, OVP, and
OCP fault flags can be blanked during soft start by setting the
appropriate bits in Register 0x0F. The UVP fault is blanked only
for the debounce time during soft start and, therefore, if the soft
start period exceeds the debounce time, the UVP fault will be
triggered and stored in the first fault ID register. A read of the
latched fault registers and the FFID register clears the falsely
triggered UVP condition.
Rev. B | Page 20 of 92
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